Patents by Inventor Olivier Lembeye
Olivier Lembeye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120887Abstract: An amplifier device having multiple amplification paths, such as a Doherty amplifier device, may include phase slope adjustment circuitry configured to adjust the frequency-dependent slope of the phase of an input carrier signal along a carrier path of the amplifier. By adjusting the phase slope of the input carrier signal in this way, the phase difference between carrier and peaking signals at an output combining node of the amplifier may be reduced, thereby reducing output power ripple of the amplifier. The phase slope adjustment circuitry may be a constant-k bandpass filter. The phase slope adjustment circuitry may have a zero-degree insertion phase at the center frequency of the amplifier. The phase slope adjustment circuitry may be implemented using surface mount inductors and capacitors.Type: ApplicationFiled: September 8, 2023Publication date: April 11, 2024Inventors: Manuel Cavarroc, Olivier Lembeye, Anthony Lamy
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Publication number: 20230361726Abstract: An RF amplifier includes at least one harmonic trap filter with an array of shunt filter legs having a non-uniform resonance frequency distribution. The harmonic trap filter is configured to suppress frequencies in a suppression frequency range that includes harmonic frequencies of carrier frequencies in a range of carrier frequencies. Each of the shunt filter legs includes a capacitor and inductor coupled in series, and an intermediate node coupled between the capacitor and the inductor. Each intermediate node of the shunt filter leg is coupled to at least one other intermediate node of another shunt filter leg of the filter with a dampening resistor. Shunt filters at or near edges of the array are configured to have lower resonance frequencies than those at or near the center of the array to suppress excess current flow at edges of the RF amplifier.Type: ApplicationFiled: February 28, 2023Publication date: November 9, 2023Inventors: Joseph Gerard Schultz, Kevin Kim, Jeffrey Kevin Jones, Vikas Shilimkar, Olivier Lembeye
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Patent number: 11784610Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Doherty amplifier module includes a first amplifier die with a first output terminal, a second amplifier die with a second output terminal, and a wideband impedance inverter circuit electrically coupled between the first and second output terminals. The wideband impedance inverter circuit includes a network of capacitors, the network of capacitors including at least a series capacitor having a positive capacitance, a first shunt circuit having a first negative capacitance, and a second shunt circuit having a second negative capacitance.Type: GrantFiled: March 3, 2021Date of Patent: October 10, 2023Assignee: NXP USA, Inc.Inventors: Anthony Lamy, Olivier Lembeye
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Patent number: 11705870Abstract: Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.Type: GrantFiled: September 17, 2020Date of Patent: July 18, 2023Assignee: NXP USA, Inc.Inventors: Xavier Hue, Olivier Lembeye, Pascal Peyrot
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Patent number: 11705872Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.Type: GrantFiled: December 4, 2020Date of Patent: July 18, 2023Assignee: NXP USA, Inc.Inventors: Jeffrey Spencer Roberts, Ning Zhu, Olivier Lembeye, Damon G. Holmes, Jeffrey Kevin Jones
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Patent number: 11277100Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.Type: GrantFiled: July 24, 2020Date of Patent: March 15, 2022Assignee: NXP USA, Inc.Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
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Publication number: 20220021343Abstract: Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.Type: ApplicationFiled: September 17, 2020Publication date: January 20, 2022Inventors: Xavier Hue, Olivier Lembeye, Pascal Peyrot
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Patent number: 11223326Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.Type: GrantFiled: July 24, 2020Date of Patent: January 11, 2022Assignee: NXP USA, Inc.Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
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Publication number: 20210281221Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Doherty amplifier module includes a first amplifier die with a first output terminal, a second amplifier die with a second output terminal, and a wideband impedance inverter circuit electrically coupled between the first and second output terminals. The wideband impedance inverter circuit includes a network of capacitors, the network of capacitors including at least a series capacitor having a positive capacitance, a first shunt circuit having a first negative capacitance, and a second shunt circuit having a second negative capacitance.Type: ApplicationFiled: March 3, 2021Publication date: September 9, 2021Inventors: Anthony Lamy, Olivier Lembeye
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Publication number: 20210175860Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.Type: ApplicationFiled: December 4, 2020Publication date: June 10, 2021Inventors: Jeffrey Spencer Roberts, Ning Zhu, Olivier Lembeye, Damon G. Holmes, Jeffrey Kevin Jones
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Patent number: 10951180Abstract: Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit is an output pre-match impedance conditioning shunt circuit, which includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The first shunt inductance comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductance, and the second shunt inductance comprises an integrated inductor coupled between the first shunt inductance and a first terminal of the shunt capacitor. The shunt capacitor is configured to provide capacitive harmonic control of an output of the transistor.Type: GrantFiled: December 6, 2018Date of Patent: March 16, 2021Assignee: NXP USA, Inc.Inventors: Pascal Peyrot, Olivier Lembeye, Enver Krvavac
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Publication number: 20210013837Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.Type: ApplicationFiled: July 24, 2020Publication date: January 14, 2021Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
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Publication number: 20200389130Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.Type: ApplicationFiled: July 24, 2020Publication date: December 10, 2020Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
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Patent number: 10763792Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.Type: GrantFiled: October 26, 2018Date of Patent: September 1, 2020Assignee: NXP USA, Inc.Inventors: Joseph Gerard Schultz, Enver Krvavac, Olivier Lembeye, Cedric Cassan, Kevin Kim, Jeffrey Kevin Jones
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Publication number: 20190190464Abstract: Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit is an output pre-match impedance conditioning shunt circuit, which includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The first shunt inductance comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductance, and the second shunt inductance comprises an integrated inductor coupled between the first shunt inductance and a first terminal of the shunt capacitor. The shunt capacitor is configured to provide capacitive harmonic control of an output of the transistor.Type: ApplicationFiled: December 6, 2018Publication date: June 20, 2019Inventors: Pascal PEYROT, Olivier LEMBEYE, Enver KRVAVAC
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Publication number: 20190140598Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.Type: ApplicationFiled: October 26, 2018Publication date: May 9, 2019Inventors: Joseph Gerard SCHULTZ, Enver KRVAVAC, Olivier LEMBEYE, Cedric CASSAN, Kevin KIM, Jeffrey Kevin JONES
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Patent number: 10211170Abstract: A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.Type: GrantFiled: August 10, 2017Date of Patent: February 19, 2019Assignee: NXP USA, INC.Inventors: Pascal Peyrot, Olivier Lembeye, Sai Sunil Mangaonkar
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Patent number: 10110178Abstract: In a system comprising a plurality of gain elements configured in parallel to one another, a harmonically tuned filter provides an isolation circuit to prevent odd-mode differential oscillations. A harmonically tuned filter comprises resistors, inductors, and capacitors (RLC) to selectively allow one or more specific harmonics to pass through the isolation circuit to suppress the odd-mode oscillation. Direct current (DC) and other non-harmonically-related frequencies do not pass through the isolation circuit. Since the resistor is used to dissipate specifically the energy of the harmonic frequencies causing the odd-mode oscillation, the current density through the resistor is much lower than the current density of a typical odd-mode resistor without a harmonically tuned filter.Type: GrantFiled: November 21, 2014Date of Patent: October 23, 2018Assignee: NXP USA, INC.Inventors: Kevin Kim, Igor Ivanovich Blednov, Olivier Lembeye, Pascal Peyrot
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Patent number: 9923526Abstract: An RF amplifier includes a harmonic filter with a plurality of shunt filter legs. The harmonic filter provides a suppressing frequency range for a harmonic frequency of a carrier frequency in a range of carrier frequencies. Each of the shunt filter legs includes capacitor, inductor, and a node coupled between the capacitor and inductor. Each node of the shunt filter leg is coupled to at least one other node of another shunt filter leg of the filter with a resistive element. The harmonic filter includes a first shunt filter leg that has a resonant frequency between the center frequency and (1/1.220) times the center frequency and a second shunt filter leg that has a resonant frequency between the center frequency and 1.220 times the center frequency.Type: GrantFiled: March 7, 2017Date of Patent: March 20, 2018Assignee: NXP USA, INC.Inventor: Olivier Lembeye
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Patent number: 9911703Abstract: A packaged RF amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying terminals. The output circuit is coupled between the first current carrying terminal and an output lead. The output circuit includes first and second inductive elements coupled in series. The first inductive element, which may be a first bondwire array or an integrated inductance, is coupled between the first current carrying terminal and a node. The second inductive element, which includes a second bondwire array, is coupled between the node and the output lead. The device also includes a shunt circuit with a shunt capacitor and a third bondwire array coupled between the first current carrying terminal and the shunt capacitor. The first and second inductive elements and the third bondwire array are configured to have a desired mutual inductance.Type: GrantFiled: October 21, 2016Date of Patent: March 6, 2018Assignee: NXP USA, INC.Inventors: Olivier Lembeye, Damon G. Holmes, Ning Zhu