Abstract: Methods are disclosed for etching a substrate. The method includes preferentially coating cover ring relative other chamber components in the processing chamber, while under vacuum, and while a substrate is not present in the processing chamber. The substrate is subsequently etched the processing chamber. After etching, the interior of the processing chamber is cleaned after the substrate has been removed.

Abstract: A method of processing a substrate includes depositing an oxide material on a substrate having a first region, a second region and a plurality of features, wherein the first region has a high feature density and the second region has a low feature density; and controlling a ratio of an etch rate of the oxide material in the first region to an etch rate of the oxide material in the second region by forming an ammonium hexafluorosilicate ((NH4)2SiF6) layer having a first thickness atop the oxide material in the first region and having a second thickness atop the oxide material in the second region.

Abstract: A method of processing a substrate includes depositing an oxide material on a substrate having a first region, a second region and a plurality of features, wherein the first region has a high feature density and the second region has a low feature density; and controlling a ratio of an etch rate of the oxide material in the first region to an etch rate of the oxide material in the second region by forming an ammonium hexafluorosilicate ((NH4)2SiF6) layer having a first thickness atop the oxide material in the first region and having a second thickness atop the oxide material in the second region.

Abstract: Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode.

Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.

Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.

Abstract: Embodiments of the technology include a semiconductor patterning method. The method may include forming a layer of masking material on regions of dielectric material above a semiconductor substrate. The method may include forming a trench through the masking material. This transformation may expose at least a portion of the dielectric material. The method may include forming a protective layer over the exposed portion of the dielectric material. The method may involve removing the masking material from the semiconductor substrate.

Abstract: Embodiments of the present invention provide an apparatus and methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one embodiment, a method of forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, wherein the trimming process further comprises supplying a trimming gas mixture including at least an oxygen containing gas, and providing a light energy in the trimming gas mixture to an edge of the substrate during the trimming process.

Abstract: Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode.