Patents by Inventor Olivier Ory
Olivier Ory has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063162Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 ?m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Applicant: STMICROELECTRONICS (TOURS) SASInventors: Olivier ORY, Christophe LEBRERE
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Patent number: 11881413Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.Type: GrantFiled: January 12, 2023Date of Patent: January 23, 2024Assignee: STMICROELECTRONICS (TOURS) SASInventors: Michael De Cruz, Olivier Ory
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Patent number: 11824028Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 ?m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.Type: GrantFiled: August 26, 2021Date of Patent: November 21, 2023Assignee: STMICROELECTRONICS (TOURS) SASInventors: Olivier Ory, Christophe Lebrere
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Patent number: 11784104Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.Type: GrantFiled: September 30, 2021Date of Patent: October 10, 2023Assignee: STMICROELECTRONICS (TOURS) SASInventors: Olivier Ory, Romain Jaillet
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Publication number: 20230178380Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.Type: ApplicationFiled: January 12, 2023Publication date: June 8, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Michael DE CRUZ, Olivier ORY
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Publication number: 20230068222Abstract: The present disclosure relates to a method for manufacturing electronic chips comprising, in order: a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed; b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate; c. forming first trenches of a first width on the side of a second face of the semiconductor substrate; d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate; e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Olivier ORY, Michael DE CRUZ
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Patent number: 11581304Abstract: The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.Type: GrantFiled: August 6, 2020Date of Patent: February 14, 2023Assignee: STMicroelectronics (Tours) SASInventor: Olivier Ory
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Patent number: 11574816Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.Type: GrantFiled: November 25, 2020Date of Patent: February 7, 2023Assignee: STMICROELECTRONICS (TOURS) SASInventors: Michael De Cruz, Olivier Ory
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Publication number: 20230021534Abstract: The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.Type: ApplicationFiled: July 6, 2022Publication date: January 26, 2023Applicant: STMICROELECTRONICS (TOURS) SASInventors: Olivier ORY, Philippe RABIER
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Publication number: 20220375840Abstract: The present disclosure relates to an electronic chip comprising a semiconductor substrate carrying at least one metal contact extending, within the thickness of the substrate, along at least one flank of the chip.Type: ApplicationFiled: May 13, 2022Publication date: November 24, 2022Applicant: STMICROELECTRONICS (TOURS) SASInventors: Olivier ORY, Michael DE CRUZ
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Patent number: 11437365Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.Type: GrantFiled: March 30, 2020Date of Patent: September 6, 2022Assignee: STMicroelectronics (Tours) SASInventors: Eric Laconde, Olivier Ory
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Patent number: 11296071Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.Type: GrantFiled: March 30, 2020Date of Patent: April 5, 2022Assignee: STMicroelectronics (Tours) SASInventors: Eric Laconde, Olivier Ory
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Patent number: 11289391Abstract: A device comprising a semiconductor substrate, an electrically-conductive layer covering the substrate, and an insulating sheath, the conductive layer being in contact with the insulating sheath on the side opposite to the substrate.Type: GrantFiled: February 26, 2020Date of Patent: March 29, 2022Assignee: STMICROELECTRONICS (TOURS) SASInventor: Olivier Ory
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Publication number: 20220068866Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 ?m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.Type: ApplicationFiled: August 26, 2021Publication date: March 3, 2022Applicant: STMICROELECTRONICS (TOURS) SASInventors: Olivier ORY, Christophe LEBRERE
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Publication number: 20220020652Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.Type: ApplicationFiled: September 30, 2021Publication date: January 20, 2022Applicant: STMICROELECTRONICS (TOURS) SASInventors: Olivier ORY, Romain JAILLET
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Patent number: 11158556Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.Type: GrantFiled: August 27, 2019Date of Patent: October 26, 2021Assignee: STMICROELECTRONICS (TOURS) SASInventors: Olivier Ory, Romain Jaillet
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Publication number: 20210175094Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.Type: ApplicationFiled: November 25, 2020Publication date: June 10, 2021Inventors: Michael DE CRUZ, Olivier ORY
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Publication number: 20210043622Abstract: The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.Type: ApplicationFiled: August 6, 2020Publication date: February 11, 2021Inventor: Olivier ORY
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Publication number: 20200321330Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.Type: ApplicationFiled: March 30, 2020Publication date: October 8, 2020Applicant: STMicroelectronics (Tours) SASInventors: Eric LACONDE, Olivier ORY
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Publication number: 20200321329Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.Type: ApplicationFiled: March 30, 2020Publication date: October 8, 2020Applicant: STMicroelectronics (Tours) SASInventors: Eric LACONDE, Olivier ORY