Patents by Inventor Olivier Tesson

Olivier Tesson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120148
    Abstract: There is provided a phase shifting device and method of manufacturing the same. The device comprises an auto-transformer comprising a primary winding configured to receive an input signal; and two secondary windings, wherein a first one of the two secondary windings is in phase with the primary winding and a second one of the two secondary windings is out of phase with the primary winding. The device also comprises a first switch coupled to an output signal of the first one of the two secondary windings of the auto-transformer; and a second switch coupled to an output signal of the second one of the two secondary windings of the auto-transformer. Output signals of the first and second switches are couplable to an output of the phase shifting device.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 11, 2024
    Inventors: Vinicius Azevedo de Souza e Vecchia, Stephane David, Olivier Tesson
  • Publication number: 20230170126
    Abstract: A transformer (100, 100?) is disclosed, comprising a first conducting element (110) having a first lobed portion (114) arranged to form a first plurality of lobes (116); and a second conducting element (120) having a second lobed portion (124) arranged to form a second plurality of lobes (126); wherein said first lobed portion (114) overlaps said second lobed portion (124) to define a plurality of enclosed areas (130). The transformer is adapted for applications requiring an autotransformer having a weak, negative magnetic coupling coefficient.
    Type: Application
    Filed: November 10, 2022
    Publication date: June 1, 2023
    Inventors: Olivier Tesson, Konstantinos Giannakidis
  • Publication number: 20230170851
    Abstract: A phase shifter (100) with controllable attenuation and a method for controlling the phase shifter is disclosed, the phase shifter (100) comprising a plurality of transmission line segments (120, 220) coupled in series, wherein each said transmission line segment (120, 220) comprises an attenuation circuit (130, 230), selectively couplable between a signal line (126, 222) of the transmission line segment (120, 220) and ground to selectively attenuate a signal propagating through the transmission line segment (120, 220). Each transmission line segment (120, 220) is switchable between a first configuration providing a first phase shift for a signal propagating through the transmission line segment (120, 220) and a second configuration providing a second phase shift, greater than said first phase shift, for a signal propagating through the transmission line segment (120, 220).
    Type: Application
    Filed: November 18, 2022
    Publication date: June 1, 2023
    Inventors: Adam Erik Waks, Olivier Tesson, Olivier Crand
  • Publication number: 20230083719
    Abstract: An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.
    Type: Application
    Filed: August 15, 2022
    Publication date: March 16, 2023
    Inventor: Olivier Tesson
  • Publication number: 20220086132
    Abstract: Mechanism to enable an Identity Provider having an authorization gateway and an authentication interface to control the download and the execution of an authentication script component managed by a broker or by a service provider.
    Type: Application
    Filed: December 3, 2019
    Publication date: March 17, 2022
    Inventors: Olivier TESSON, Patrick GEORGE
  • Patent number: 11201113
    Abstract: An integrated circuit comprising a semiconductor substrate and a passive coupler located on the substrate. The coupler includes a solenoid. The coupler also includes a signal line passing through the solenoid. A method of making an integrated circuit. The method includes providing a semiconductor substrate and forming a passive coupler in a metallization stack on the substrate. Forming the passive coupler in the metallization stack on the substrate includes forming one or more windings of the solenoid using patterned metal features in a plurality of metal layers of the metallization stack. Forming the passive coupler in the metallization stack on the substrate also includes forming a signal line using one or more patterned metal features in one or more metal layers of the metallization stack. The signal line passes through the solenoid.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP B.V.
    Inventor: Olivier Tesson
  • Publication number: 20210359388
    Abstract: A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 18, 2021
    Inventors: Olivier Tesson, Mustafa Acar
  • Publication number: 20200075485
    Abstract: An integrated circuit comprising a semiconductor substrate and a passive coupler located on the substrate. The coupler includes a solenoid. The coupler also includes a signal line passing through the solenoid. A method of making an integrated circuit. The method includes providing a semiconductor substrate and forming a passive coupler in a metallization stack on the substrate. Forming the passive coupler in the metallization stack on the substrate includes forming one or more windings of the solenoid using patterned metal features in a plurality of metal layers of the metallization stack. Forming the passive coupler in the metallization stack on the substrate also includes forming a signal line using one or more patterned metal features in one or more metal layers of the metallization stack. The signal line passes through the solenoid.
    Type: Application
    Filed: July 26, 2019
    Publication date: March 5, 2020
    Inventor: Olivier Tesson
  • Patent number: 10403540
    Abstract: An integrated circuit for a packaged device is proposed. The circuit comprises: a circuit having first and second electromagnetic radiating elements fabricated on a die; a package substrate comprising an upper surface and a lower surface; and a grounding layer provided on the lower surface of the package substrate, the grounding layer being adapted to connect to a grounding plane of a printed circuit board. The die is mounted on the upper surface of the package substrate. The grounding layer comprises a void, at least a portion of the void being positioned so as to at least partially electromagnetically isolate the first electromagnetic radiating element from the second electromagnetic radiating element.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: September 3, 2019
    Assignee: NXP B.V.
    Inventors: Patrice Gamand, Olivier Tesson
  • Patent number: 10217671
    Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Thomas Francois
  • Patent number: 10217735
    Abstract: A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Thomas Francois
  • Publication number: 20180211882
    Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.
    Type: Application
    Filed: January 9, 2018
    Publication date: July 26, 2018
    Inventors: Olivier Tesson, Thomas Francois
  • Publication number: 20170373054
    Abstract: A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.
    Type: Application
    Filed: May 16, 2017
    Publication date: December 28, 2017
    Inventors: Olivier Tesson, Thomas Francois
  • Patent number: 9721844
    Abstract: A semiconductor device comprising a switch and a method of making the same. The device has a layout that includes one or more rectangular unit cells. Each unit cell includes a gate that divides the unit cell into four corner regions. Each unit cell also includes a source comprising first and second source regions located in respective opposite corner regions of the unit cell. Each unit cell further includes a drain comprising first and second drain regions located in respective opposite corner regions of the unit cell. Each unit cell also includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the gate, source and drain.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 1, 2017
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Hamza Nijjari
  • Patent number: 9704647
    Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Magali Duplessis, Olivier Tesson
  • Publication number: 20160247880
    Abstract: A semiconductor device comprising a switch and a method of making the same. The device has a layout that includes one or more rectangular unit cells. Each unit cell includes a gate that divides the unit cell into four corner regions. Each unit cell also includes a source comprising first and second source regions located in respective opposite corner regions of the unit cell. Each unit cell further includes a drain comprising first and second drain regions located in respective opposite corner regions of the unit cell. Each unit cell also includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the gate, source and drain.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 25, 2016
    Inventors: Olivier Tesson, Hamza Nijjari
  • Patent number: 9391214
    Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 12, 2016
    Assignee: NXP B.V.
    Inventors: Olivier Tesson, Mathieu Perin, Laure Rolland du Roscoat
  • Patent number: 9305697
    Abstract: An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 5, 2016
    Assignee: NXP, B.V.
    Inventor: Olivier Tesson
  • Patent number: 9160052
    Abstract: A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 13, 2015
    Assignee: NXP, B.V.
    Inventors: Olivier Tesson, Patrice Gamand, Sidina Wane
  • Publication number: 20150270061
    Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.
    Type: Application
    Filed: April 7, 2015
    Publication date: September 24, 2015
    Inventors: Magali Duplessis, Olivier Tesson