Patents by Inventor Olivier Tesson
Olivier Tesson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9391214Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.Type: GrantFiled: March 2, 2015Date of Patent: July 12, 2016Assignee: NXP B.V.Inventors: Olivier Tesson, Mathieu Perin, Laure Rolland du Roscoat
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Patent number: 9305697Abstract: An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil.Type: GrantFiled: December 17, 2014Date of Patent: April 5, 2016Assignee: NXP, B.V.Inventor: Olivier Tesson
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Patent number: 9160052Abstract: A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.Type: GrantFiled: February 28, 2013Date of Patent: October 13, 2015Assignee: NXP, B.V.Inventors: Olivier Tesson, Patrice Gamand, Sidina Wane
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Publication number: 20150270061Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.Type: ApplicationFiled: April 7, 2015Publication date: September 24, 2015Inventors: Magali Duplessis, Olivier Tesson
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Patent number: 9136061Abstract: A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighboring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.Type: GrantFiled: July 29, 2013Date of Patent: September 15, 2015Assignee: NXP, B.V.Inventors: Olivier Tesson, Laure Rolland du Roscoat
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Publication number: 20150255630Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.Type: ApplicationFiled: March 2, 2015Publication date: September 10, 2015Inventors: Olivier Tesson, Mathieu Perin, Laure Rolland du Roscoat
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Patent number: 9082738Abstract: A semiconductor package, comprises an encapsulant which contains a semiconductor substrate, the package lower side being mountable on a surface. The semiconductor substrate backside is in close proximity of the semiconductor package lower side for improved thermal conductivity to the surface. The active side of the semiconductor substrate, facing the upper side of the semiconductor package, has a plurality of die contacts. A plurality of electrically conductive interconnects are connected to the die contacts and extend to the lower side of the semiconductor package for connecting the die contacts to the surface.Type: GrantFiled: December 18, 2012Date of Patent: July 14, 2015Assignee: NXP, B.V.Inventors: Pascal Talbot, Olivier Tesson
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Patent number: 9064627Abstract: The invention proposes a radio frequency circuit which comprises a transformer with a first primary circuit, a second primary circuit, and a secondary circuit, the secondary circuit comprising an integrated first inductor, this first inductor being positioned, on an axis orthogonal to a surface of the circuit, between an integrated second and third inductor respectively comprised in the first primary circuit and second primary circuit.Type: GrantFiled: October 12, 2010Date of Patent: June 23, 2015Assignees: ST-ERICSSON SA, ST-ERICSSON (FRANCE) SASInventors: Christophe Cordier, Thomas Francois, Olivier Tesson
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Publication number: 20150170824Abstract: An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil.Type: ApplicationFiled: December 17, 2014Publication date: June 18, 2015Inventor: Olivier Tesson
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Patent number: 9048021Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.Type: GrantFiled: May 4, 2011Date of Patent: June 2, 2015Assignee: NXP B.V.Inventors: Magali Duplessis, Olivier Tesson
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Publication number: 20150070240Abstract: An integrated circuit for a packaged device is proposed. The circuit comprises: a circuit having first and second electromagnetic radiating elements fabricated on a die; a package substrate comprising an upper surface and a lower surface; and a grounding layer provided on the lower surface of the package substrate, the grounding layer being adapted to connect to a grounding plane of a printed circuit board. The die is mounted on the upper surface of the package substrate. The grounding layer comprises a void, at least a portion of the void being positioned so as to at least partially electromagnetically isolate the first electromagnetic radiating element from the second electromagnetic radiating element.Type: ApplicationFiled: September 8, 2014Publication date: March 12, 2015Inventors: Patrice Gamand, Olivier Tesson
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Publication number: 20140036406Abstract: A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighbouring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.Type: ApplicationFiled: July 29, 2013Publication date: February 6, 2014Applicant: NXP B.V.Inventors: Olivier Tesson, Laure Rolland du Roscoat
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Publication number: 20130229239Abstract: A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.Type: ApplicationFiled: February 28, 2013Publication date: September 5, 2013Applicant: NXP B.V.Inventors: Olivier Tesson, Patrice Gamand, Sidina Wane
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Patent number: 8258916Abstract: The present invention relates in general to the field of integrated circuits, and more specifically to a meander resistor. Basically, a meander resistor can be considered as a bar resistor with the exception of the corner squares (right-angle bends). The Electrostatic Discharge (ESD) sensitivities of on-chip resistors can be a problem for both electronic manufactures and electronic component users. As others components, passive devices are known to be susceptible to ESD events. The context of this invention is to improve the reliability of the resistors during an ESD event. An ESD stress means that high current and high voltage levels are applied to the device. The device has to be able to dissipate this energy without failure.Type: GrantFiled: July 2, 2009Date of Patent: September 4, 2012Assignee: NXP B.V.Inventors: Olivier Tesson, Frédéric Francois Barbier
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Publication number: 20120194403Abstract: The invention proposes a radio frequency circuit which comprises a transformer with a first primary circuit, a second primary circuit, and a secondary circuit, the secondary circuit comprising an integrated first inductor, this first inductor being positioned, on an axis orthogonal to a surface of the circuit, between an integrated second and third inductor respectively comprised in the first primary circuit and second primary circuit.Type: ApplicationFiled: October 12, 2010Publication date: August 2, 2012Applicants: ST-ERICSSON SA, ST-ERICSSON (FRANCE) SASInventors: Christophe Cordier, Thomas Francois, Olivier Tesson
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Publication number: 20110273258Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.Type: ApplicationFiled: May 4, 2011Publication date: November 10, 2011Applicant: NXP B.V.Inventors: Magali Duplessis, Olivier Tesson
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Publication number: 20110241820Abstract: The present invention relates in general to the field of integrated circuits, and more specifically to a meander resistor. Basically, a meander resistor can be considered as a bar resistor with the exception of the corner squares (right-angle bends). The Electrostatic Discharge (ESD) sensitivities of on-chip resistors can be a problem for both electronic manufactures and electronic component users. As others components, passive devices are known to be susceptible to ESD events. The context of this invention is to improve the reliability of the resistors during an ESD event. An ESD stress means that high current and high voltage levels are applied to the device. The device has to be able to dissipate this energy without failure.Type: ApplicationFiled: July 2, 2009Publication date: October 6, 2011Applicant: NXP B.V.Inventors: Olivier Tesson, Frédéric Francois Barbier
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Publication number: 20100316911Abstract: A multilayer structure, in particular a trench capacitor, is provided comprising a patterned layer structure comprising trenches, and a first electrode, wherein the patterned layer structure comprises a FASS-curve structure, and wherein at least parts of the first electrode are formed on the FASS-curve structure.Type: ApplicationFiled: October 20, 2008Publication date: December 16, 2010Applicant: IPDIAInventors: Olivier Tesson, Francois LeCornec