Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

Abstract: A bipolar transistor includes a first PN junction and a second PN junction. A first gate is located on the first PN junction. A second gate is located on the second PN junction.

Abstract: The present disclosure relates to a process that includes the simultaneous formation of a first transistor in and on a first region of a substrate, of a second transistor in and on a second region of the substrate, of a third transistor in and on a third region of the substrate and of a memory cell in and on a fourth region of the substrate. The method includes the following successive steps: forming a first gate stack on the first region, a second gate stack on the second region, a third gate stack on the third region and a fourth stack on line with the fourth region; simultaneously etching a part of the third gate stack and the fourth stack the first and the second gate stacks being protected with a first mask; and simultaneously etching the first and the second gate stacks, the third gate stack and the fourth region of the semiconductor substrate being protected with a second mask.

Abstract: An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.

Abstract: A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

Abstract: A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

Abstract: The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.

Abstract: The semiconductor device of a silicon on insulator type includes a NMOS transistor in a P-type well of the carrier substrate, a PMOS transistor in an N-type well of the carrier substrate, and a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor. The neutral back bias condition is achieved when a first non-zero negative voltage is applied to the P-type well and a first non-zero positive voltage is applied to the N-type well. The NMOS and PMOS transistors are configured to have nominal threshold voltages in the neutral back bias condition.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.