Abstract: The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg?0.04?0.005*Xge<Wf1<Wfmg?0.03?0.005*Xge.

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.

Abstract: The invention relates to a shoe, especially for sport or leisure, comprising an upper, a sole and a lacing device having at least one clamping strip passing through a space arranged at the level of the sole and a clamping element. The clamping element is attached, on the one hand, to a first end of the clamping strip and, on the other hand, to a holding zone placed at the rear of the shoe. The second end of the clamping strip, passing through the clamping element comprises an attachment device on the upper, allowing the fixing of the strip. Cooperation exists between the clamping strip, the clamping element and the holding zone causing tensing of the upper at the level of the instep and the articulation above the heel.

Abstract: The invention relates to a shoe, especially for sport or leisure, comprising an upper, a sole and a lacing device having at least one clamping strip passing through a space arranged at the level of the sole and a clamping element. The clamping element is attached, on the one hand, to a first end of the clamping strip and, on the other hand, to a holding zone placed at the rear of the shoe. The second end of the clamping strip, passing through the clamping element comprises an attachment device on the upper, allowing the fixing of the strip. Cooperation exists between the clamping strip, the clamping element and the holding zone causing tensing of the upper at the level of the instep and the articulation above the heel.