Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

Abstract: Circuitry comprises memory access circuitry to control memory access by mapping virtual memory addresses in a virtual memory address space to physical memory addresses in a physical memory address space, the memory access circuitry being configured to provide a sparse mapping in which a mapped subset of the virtual memory address space is mapped to physical memory while an unmapped subset of the virtual memory address space is unmapped, the memory access circuitry being configured to discard write operations to virtual memory addresses in the unmapped subset of the virtual memory address space and processing circuitry to execute program code defining a processing operation to generate processed data and to store the processed data in a memory region of the virtual memory address space applicable to that processing operation; detector circuitry to detect whether the memory region is entirely within the unmapped subset of the virtual memory address space.

Abstract: A method of operating a cache system is disclosed. When it is desired to evict a cache entry from the cache, a cache entry to evict from the cache is selected using an age of any compression block that the cache is caching data for, and the selected cache entry is evicted from the cache.

Abstract: When generating a render output in which primitives to be rendered are to be clipped against a user-defined clip plane defined for the render output, and a primitive to be rendered is intersected by a user-defined clip plane defined for the render output, an edge representing the intersection of the primitive with the user-defined clip plane is determined. The rasteriser, when rasterising the primitive, then tests one or more regions of the render output being generated against the determined edge representing the intersection of the primitive with the user-defined clip plane to determine whether the region or regions should not be rendered for the primitive on the basis of the user-defined clip plane.

Abstract: Address translation circuitry (20) converts virtual addresses into physical addresses with reference to intermediate level and final level page tables. Final level descriptors within final level page tables identify address translation data for an associated region of memory. Intermediate level descriptors within intermediate level page tables identify intermediate address translation data used to identify an associated page table at a next level of the page tables. Page table update circuitry (35) maintains state information within each final and intermediate level descriptor, and updates the state information from a clean state to a dirty state: in the final level descriptors to indicate that a modification of content of the associated memory region is permitted; in the intermediate level descriptors to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor.

Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry including, inter alia, at least an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents, and an indication of whether the group of fragments that the list entry represents is eligible to undergo particular processing operations. The coverage information and eligibility information for the list entries is then used to control the processing of fragments for sub-regions of a tile, in such a way as to ensure that processing order dependencies are enforced and met.

Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.

Abstract: To suspend the processing for a group of one or more execution threads currently executing a shader program for an output being generated by a graphics processor, the issuing of shader program instructions for execution by the group of one or more execution threads is stopped, and any outstanding register-content affecting transactions for the group of one or more execution threads are allowed to complete. Once all outstanding register-content affecting transactions for the group of one or more execution threads have completed, the content of the registers associated with the threads of the group of one or more execution threads, and a set of state information for the group of one or more execution threads, including at least an indication of the last instruction in the shader program that was executed for the threads of the group of one or more execution threads, are stored to memory.

Abstract: A data processing system includes a cache system configured to transfer data stored in the memory system to a processor and to transfer data from the processor to the memory system. The cache system comprises a cache and a data encoder associated with the cache that is configured to encode uncompressed data from the cache for storing in the memory system in a compressed format, and decode compressed data from the memory system for storing in the cache in an uncompressed format.

Abstract: Aspects of the present disclosure relate to an apparatus comprising graphics data receiver circuitry, rendering circuitry and render feedback circuitry. Graphics data comprising tiles of texture mipmap data is received and rendered to produce a rendered output, based on a used set of tiles. An intermediate representation of the used set is generated in the form of a bitmap. Based on this, a z-ordering is applied to valid bits of bitmap elements to generate a final representation of the used set.

Abstract: A data processing system comprises a processor operable to generate arrays of data. The processor comprises one or more local buffers configured to store data generated by the processor locally to the processor prior to that data being written out from the processor to memory. The processor generates data elements of an array of data and stores the data elements in the one or more local buffers. When a set of data elements that corresponds to less than an entire region of plural separate regions that the array of data is divided into is to be written from the one or more local buffers to memory, the processor may encode the set of data elements so as to produce an encoded block of data and store the encoded block of data in memory.

Abstract: When generating a render output in which primitives to be rendered are to be clipped against a user-defined clip plane defined for the render output, and a primitive to be rendered is intersected by a user-defined clip plane defined for the render output, an edge representing the intersection of the primitive with the user-defined clip plane is determined. The rasteriser, when rasterising the primitive, then tests one or more regions of the render output being generated against the determined edge representing the intersection of the primitive with the user-defined clip plane to determine whether the region or regions should not be rendered for the primitive on the basis of the user-defined clip plane.

Abstract: A method of operating a cache system is disclosed. An update to an entry in one cache of the cache system triggers updates to plural related entries in another cache of the cache system. The entries may be related to each other by virtue of caching data for the same compression block.

Abstract: A method of operating a cache system is disclosed. Information indicating a link between associated header and payload cache entries is maintained. The link information may be used to reduce cache coherency traffic.

Abstract: A method of operating a cache system is disclosed. Different entries in the same cache of the cache system are addressed using different address domains. The different address domains may be associated with different data types that are cached by the cache.

Abstract: In a data processing system comprising a cache system configured to transfer data stored in a memory system to a processor and vice-versa, a processing unit operable to read data from a cache of the cache system can send a read request for data to the cache. The cache system, in response to the read request, determines whether the requested data is present in the cache. When the requested data is present in the cache, the cache system returns the data from the cache to the processing unit and invalidates the entry for the data in the cache. When the requested data is not present in the cache, the cache system returns an indication of that to the processing unit, without the cache system sending a request for the data towards the memory system.

Abstract: Circuitry comprises memory access circuitry to control memory access by mapping virtual memory addresses in a virtual memory address space to physical memory addresses in a physical memory address space, the memory access circuitry being configured to provide a sparse mapping in which a mapped subset of the virtual memory address space is mapped to physical memory while an unmapped subset of the virtual memory address space is unmapped, the memory access circuitry being configured to discard write operations to virtual memory addresses in the unmapped subset of the virtual memory address space and processing circuitry to execute program code defining a processing operation to generate processed data and to store the processed data in a memory region of the virtual memory address space applicable to that processing operation; detector circuitry to detect whether the memory region is entirely within the unmapped subset of the virtual memory address space.

Abstract: A graphics processing system is disclosed having a cache system (24) arranged between memory (23) and the graphics processor (20), the cache system comprising a first cache (53) for transferring data to and from the graphics processor (20) and a second cache (54) arranged and configured to transfer data between the first cache (53) and memory (23). When data is to be written from the first cache (53) to memory (23), a cache controller (55) determines a data type of the data and, in dependence on the data type, either causes the data to be written into the second cache (54) without writing the data to memory (23), or causes the data to be written to memory (23) without storing the data in the second cache (54). In embodiments the second cache (54) is write-only allocated.

Abstract: A data processing system is provided comprising a cache system configured to transfer data between a processor and memory system. The cache system comprises a cache. When a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the block of data is stored into a group of one or more cache lines of the cache and the associated compression metadata for the compressed block of data is provided as separate side band data.

Abstract: A graphics processor comprising a rasteriser, a renderer, and a fragment dependency manager, and a method of operating a graphics processor. The fragment dependency manager is operable to maintain plural queues, where each queue corresponds to a respective set of plural sets of one or more sampling points that an array of sampling points is divided into, and wherein each queue entry is indicative of one or more fragments that when processed by the renderer will produce rendered fragment data for one or more of the sampling points of the set of one or more sampling points to which the queue corresponds.