Abstract: A tile-based graphics processor performs first and second processing passes to generate a render output. The first processing pass generates data that is used in the second processing pass to determine which primitives to process for which rendering tiles. The first processing pass is performed by a geometry processing control unit assembling primitives, and one or more programmable processing units transforming geometry data defining the primitives, and processing the transformed geometry data to generate the data.

Abstract: A data processing system comprises a processor that generates data elements of an array of data and stores the data elements in the one or more local buffers. When a set of data elements that corresponds to less than an entire region of plural separate regions that the array of data is divided into is to be written from the one or more local buffers to memory, the processor may encode the set of data elements so as to produce an encoded block of data and store the encoded block of data in memory by: writing body data to one of a first body buffer and a second body buffer, wherein the set of data elements is encoded using a first encoding for which header information descriptive of the body data will be independent of the values of the data elements being encoded.

Abstract: A method of managing write-after-read (WAR) hazards in a graphics processor. A host processor when preparing a graphics processor command stream can identify possible WAR hazards between rendering jobs for example by detecting layout transitions and insert a suitable barrier into the graphics processor command stream. The graphics processor when encountering such a barrier can then determine whether it is possible to ignore the barrier and allow rendering jobs to be processed concurrently.

Abstract: When performing a sequence of rendering jobs, rendering tasks for separate rendering jobs are permitted to overlap within the graphics processor's processing (shader) cores. A record is maintained of which rendering tasks are currently being processed by the graphics processor's processing (shader) cores which record can then be used to enforce any data (processing) dependencies between different rendering jobs.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced. In particular, there is disclosed a mechanism for suspending the sequence of rendering jobs (so that it may subsequently be resumed).

Abstract: A method of operating a graphics processor when performing a certain sequence of rendering jobs that produces a series of progressively lower resolution versions of the same render output comprising issuing rendering tasks for different rendering jobs concurrently and controlling processing for a later rendering job using a respective ‘task completion status’ data structure associated with the earlier rendering job on which it depends, wherein the looking up of respective entries in the ‘task completion status’ data structure takes into account the change in resolution between the first, earlier rendering job and the second, later rendering job.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks for different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks are enforced.

Abstract: A processing element is configured to approximate a transcendental function. The processing element comprises an input storage and a look-up storage. The processing element obtains floating-point input data from the input storage representing having an input exponent value and an input mantissa value. The processing element looks up approximation parameters and an output exponent value from the look-up storage, wherein each group of approximation parameters and output exponent value are stored in the look-up storage in association with a respective range of a plurality of ranges that are defined by the input exponent value and the input mantissa value. The ranges cover values of the input exponent value and input mantissa value such that the output exponent value associated with each range does not change by more than a predetermined number. An approximation function is evaluated that approximates the transcendental function based on the looked-up approximation parameters and output exponent.

Abstract: A data processor comprising an execution engine 51 for executing programs for execution threads and one or more caches 48, 49 operable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unit 54 configured to monitor the operation of the caches 48, 49 during execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.

Abstract: When performing rendering in a tile-based graphics processor that comprises plural rendering processors, different regions of the render output are allocated to different ones of the rendering processors for processing. The processing of the render output is tracked to determine when a portion of the render output that is still to be allocated to the rendering processors for processing falls below a threshold, and when it is determined that a portion of the render output that is still to be allocated to the rendering processors for processing falls below the threshold, smaller regions of the render output are thereafter allocated to the rendering processors for processing.

Abstract: Disclosed is a method of evaluating trigonometric functions in floating point arithmetic. In particular, a range reduction operation is performed to reduce the input argument x into a desired reduced ranges of values within which the trigonometric function is to be evaluated. The range reduction involves a step of computing the product of the input argument x and R, wherein R is an approximation to m/pi (with m=2, for example). The value for R is obtained as a sum of terms R0+R1+ . . . and the value of the first term R0 is configured to ensure that the expression xR0 modulo 4 can be evaluated without floating point rounding error. This can then provide an improved graphics processor operation.

Abstract: Address translation circuitry (20) converts virtual addresses into physical addresses with reference to intermediate level and final level page tables. Final level descriptors within final level page tables identify address translation data for an associated region of memory. Intermediate level descriptors within intermediate level page tables identify intermediate address translation data used to identify an associated page table at a next level of the page tables. Page table update circuitry (35) maintains state information within each final and intermediate level descriptor, and updates the state information from a clean state to a dirty state: in the final level descriptors to indicate that a modification of content of the associated memory region is permitted; in the intermediate level descriptors to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor.

Abstract: An apparatus, a computer-readable medium, a system, a chip-containing product and a method are provided relating to floating point arithmetic, wherein a combined arithmetic operation with respect to three input floating point values is performed. The combined arithmetic operation comprises a rounded first arithmetic operation on the first and second input floating point values generating a rounded first arithmetic result and a rounded second arithmetic operation on the rounded first arithmetic result and the third input floating point value to generate a final rounded result of the combined arithmetic operation. When a shift operation on a non-zero mantissa of the third input floating point value generates a zero-value shifted mantissa, the zero-value shifted mantissa is adjusted to become non-zero.

Abstract: A method of operating a cache system is disclosed. Different entries in the same cache of the cache system are addressed using different address domains. The different address domains may be associated with different data types that are cached by the cache.

Abstract: A data processing system includes an external memory system, a processor and an internal memory system. The internal memory system includes an internal memory that stores data for use by the processor when performing data processing operations. The internal memory system also includes a data encoder associated with the internal memory. The data encoder reads data from the external memory system to the data encoder and returns the data to the external memory system from the data encoder, without storing the data in the internal memory.

Abstract: The present disclosure relates to a data processing apparatus comprising: instruction decode circuitry to decode instructions; processing circuitry to execute said instructions decoded by said instruction decode circuitry, said processing circuitry comprising fused-multiply-accumulate, FMA, circuitry to respond to a fused-multiply-accumulate, FMA, instruction decoded by said instruction decoder, said FMA instruction specifying a first floating-point operand (a), a second floating-point operand (b) and a third floating-point operand (c); and an operand storage module operable to store said first floating-point operand, said second floating-point operand, and said third floating-point operand, wherein, responsive to said FMA instruction, said FMA circuitry is configured to: perform denormal detection on said first floating-point operand, said second floating-point operand and said third floating-point operand to determine if one or more of said first floating-point operand, said second floating-point operand or

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. Processing of one or more vertex attributes may be omitted during the first, pre-pass operation.

Abstract: A graphics processor comprising a rasteriser, a renderer, and a fragment dependency manager, and a method of operating a graphics processor. The fragment dependency manager is operable to maintain plural queues, where each queue corresponds to a respective set of plural sets of one or more sampling points that an array of sampling points is divided into, and wherein each queue entry is indicative of one or more fragments that when processed by the renderer will produce rendered fragment data for one or more of the sampling points of the set of one or more sampling points to which the queue corresponds.

Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.