Abstract: A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.

Abstract: A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for seed generation. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes a random seed generation circuit that generates a random seed. A scrambler component includes a deterministic seed generation circuit that generates a deterministic seed based on a physical address of a memory element for storing data. A scrambler component includes a computation circuit that forms a computed seed based on a random seed and a deterministic seed. Data is scrambled using a computed seed before data is stored.

Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells, one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to encode data with a code rate prior to storage in the set of non-volatile memory cells, the code rate selected from two or more code rates according to one or more predictive indicators received with the data, the one or more predictive indicators relating to expected conditions for storage of the data in the set of non-volatile memory cells

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Abstract: Technology is described herein for learning parameters for a parameterized iterative message passing decoder, and to a corresponding parameterized iterative message passing decoder. Learning the parameters may adapt the decoder to statistical dependencies introduced by the specific code's graph. Taking into account the statistical dependencies may allow the code to be shorter and/or denser. Note that the statistical dependencies in the graph may be extremely complex. Machine learning may be used to learn the parameters. The parameters may be learned when decoding data stored in the memory device. Learning the parameters may adapt the decoder to properties of data stored in the memory device, physical properties of the memory device, and/or patterns in host data.

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

Abstract: A storage system and method for predictive block allocation for efficient garbage collection are provided. One method involves determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.

Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.

Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

Abstract: A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.

Abstract: A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Abstract: Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high throughput. Programming conditions are adaptively changed at the sub-codeword level in order to keep power supply current of the memory system within a target. In one embodiment, a chunk of data that corresponds to a sub-codeword is written while consuming lower than normal programming current in order to keep power supply current within a target. The relatively low programming current may increase the expected raw BER. However, other portions of the codeword can be written with a higher than normal programming current, which results in a lower expected bit raw error rate for the memory cells that store that portion.

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

Abstract: A device includes a memory a memory configured to store syndromes. The device also includes a pipelined data processing unit and routing circuitry. The routing circuitry includes a first input coupled to the memory and includes a second input coupled to an output of the pipelined data processing unit.

Abstract: A device includes a memory a memory configured to store syndromes. The device also includes a pipelined data processing unit and routing circuitry. The routing circuitry includes a first input coupled to the memory and includes a second input coupled to an output of the pipelined data processing unit.