Abstract: A data storage device includes a memory and a decoder. In one embodiment, the decoder includes a bit-flipping stage and a second decoding stage. The decoder is configured to receive data from the memory and to process the received data at the bit-flipping stage to generate first stage result data. The data corresponds to an error correction coding (ECC) codeword of an ECC code. The data is processed at the bit-flipping stage based on parity checks of the error correction code (ECC) code that are not satisfied by the data. The data is processed at the bit-flipping stage without first attempting to decode the received data at the second decoding stage. The decoder is further configured to provide the first stage result data to an input of the second decoding stage and to initiate decoding at the second decoding stage at least partially based on the first stage result data.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Abstract: An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method may include determining whether participating bits for a particular parity-check equation from the plurality of parity check equations satisfy the particular parity-check equation. The method may further include determining, based on whether the particular parity-check equation is satisfied, a magnitude of a reliability modification to one or more reliability values associated with at least one of the participating bits. The method may also include modifying the one or more reliability values by the magnitude of the reliability modification.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Abstract: An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.

Abstract: A data storage device includes a memory and a decoder. In one embodiment, the decoder includes a bit-flipping stage and a second decoding stage. The decoder is configured to receive data from the memory and to process the received data at the bit-flipping stage to generate first stage result data. The data corresponds to an error correction coding (ECC) codeword of an ECC code. The data is processed at the bit-flipping stage based on parity checks of the error correction code (ECC) code that are not satisfied by the data. The data is processed at the bit-flipping stage without first attempting to decode the received data at the second decoding stage. The decoder is further configured to provide the first stage result data to an input of the second decoding stage and to initiate decoding at the second decoding stage at least partially based on the first stage result data.

Abstract: Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data.

Abstract: An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method may include determining whether participating bits for a particular parity-check equation from the plurality of parity check equations satisfy the particular parity-check equation. The method may further include determining, based on whether the particular parity-check equation is satisfied, a magnitude of a reliability modification to one or more reliability values associated with at least one of the participating bits. The method may also include modifying the one or more reliability values by the magnitude of the reliability modification.

Abstract: An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.

Abstract: Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data.

Abstract: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.

Abstract: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.