Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Abstract: Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.

Abstract: Alignment markers are created on a carrier wafer prior to attachment of integrated circuit dies to the carrier wafer. The alignment markers can be used in aligning integrated circuit dies to the carrier wafer during attachment of the integrated circuit dies to the carrier wafer. A reconstituted wafer can be created from the integrated circuit dies attached to the carrier wafer and the alignment markers are part of the reconstituted wafer. The alignment markers can further be used to align a wafer bonding layer to the reconstituted wafer. The wafer bonding layer can be used in attaching the reconstituted wafer to an interposer, another wafer, or another microelectronic structure. The alignment markers are located outside an outer lateral boundary of the integrated circuit dies (such as between integrated circuit dies) and are not connected to any metal lines in the integrated circuit dies in the reconstituted wafer.

Abstract: Input/output (I/O) routing from one integrated circuit die to other integrated circuit dies in an integrated circuit component comprising heterogeneous and vertically stacked die is made from the top and bottom surfaces of the integrated circuit die to the other dies. Die-to-die I/O routing from the die to laterally adjacent die is made from the top surface of the die via one or more redistribution layers. Die-to-die routing from the die to vertically adjacent die is made via hybrid bonding on the bottom surface of the die. Embedded bridges or chiplets or not used for die-to-die I/O routing, which can free up space for more through-dielectric vias to provide power and ground connections to the die, which can provide for improved power delivery.

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICS. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

Abstract: In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

Abstract: An apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a fiducial having a length size greater than a width size of the fiducial, wherein the fiducial comprises at least one first area and at least one second area, wherein the at least one first area is to stop light from a light source and the at least one second area is to pass light from the light source during a determination of an alignment between the first integrated circuit device and a second integrated circuit device.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.

Abstract: An architecture for v-groove fiber attach for a photonic integrated circuit (PIC). The architecture is characterized by a PIC with a thickness of less than 100 microns. A carrier layer is attached to the non-active surface of the PIC and v-grooves are etched into the active surface of the PIC wafer. The carrier layer functions as an etch stop during the etching of the v-grooves, thereby becoming a floor for the v-grooves and enabling the v-grooves to extend to a depth equal to the thickness of the PIC. The carrier layer can be a glass layer. The carrier layer can also be an electronic integrated circuit (EIC).

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.