Patents by Inventor Omkar G. Karhade
Omkar G. Karhade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210287974Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.Type: ApplicationFiled: September 29, 2016Publication date: September 16, 2021Applicant: Intel CorporationInventors: Omkar G. Karhade, Nachiket R. Raravikar, Sandeep B. Sane
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Patent number: 11114388Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: GrantFiled: February 20, 2019Date of Patent: September 7, 2021Assignee: INTEL CORPORATIONInventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
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Publication number: 20210272905Abstract: Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Omkar G. Karhade, Debendra Mallik, Nitin A. Deshpande, Amruthavalli Pallavi Alur
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Publication number: 20210066265Abstract: Disclosed herein are tunable capacitor arrangements in integrated circuit (IC) package substrates, as well as related methods and devices. For example, in some embodiments, an IC package substrate may include a first embedded capacitor, a second embedded capacitor, and a fuse electrically coupled between the first embedded capacitor and the second embedded capacitor such that when the fuse is in a closed state, the first embedded capacitor and the second embedded capacitor are connected in parallel, and when the fuse is in an open state, the first embedded capacitor and the second embedded capacitor are not connected in parallel.Type: ApplicationFiled: August 28, 2019Publication date: March 4, 2021Applicant: Intel CorporationInventors: Feras Eid, Aleksandar Aleksov, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan, Sivakumar Nagarajan, Nitin A. Deshpande, Omkar G. Karhade, William James Lambert
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Publication number: 20200350181Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: ApplicationFiled: June 29, 2020Publication date: November 5, 2020Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Debendra MALLIK, Bassam M. ZIADEH, Yoshihiro TOMITA
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Patent number: 10797000Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: GrantFiled: January 22, 2019Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Nitin A. Deshpande, Omkar G. Karhade
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Patent number: 10741419Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: GrantFiled: July 18, 2019Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
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Publication number: 20200203839Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna board may include a plurality of antenna patches coupled to a dielectric material and a plurality of pedestals extending from a face of the dielectric material and at least partially embedded in the dielectric material.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: Omkar G. Karhade, William James Lambert, Xiaoqian Li, Nitin A. Deshpande, Debendra Mallik
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Patent number: 10672626Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.Type: GrantFiled: March 24, 2017Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Aditya S. Vaidya, Nachiket R. Raravikar, Eric J. Li
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Publication number: 20190341271Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Debendra MALLIK, Bassam M. ZIADEH, Yoshihiro TOMITA
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Publication number: 20190330051Abstract: Embodiments include a microelectronic device package structure having a die on a substrate, where a first side of the die is electrically coupled to the substrate, and a second side of the die is covered with a first material having a first thermal conductivity. A second material is adjacent to a sidewall of the die and adjacent to a sidewall of the first material. The second material has second thermal conductivity, smaller than the first thermal conductivity. The second material may have mechanical and/or underfill properties superior to those of the first material. Together, the two materials may provide a package structure having enhanced thermal and mechanical performance.Type: ApplicationFiled: April 25, 2018Publication date: October 31, 2019Applicant: Intle CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande
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Publication number: 20190279960Abstract: Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.Type: ApplicationFiled: December 14, 2016Publication date: September 12, 2019Applicant: Intel CorporationInventors: Omkar G. Karhade, Edvin Cetegen, Sandeep B. Sane
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Patent number: 10403512Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.Type: GrantFiled: February 19, 2018Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
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Publication number: 20190259713Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: ApplicationFiled: February 20, 2019Publication date: August 22, 2019Applicant: INTEL CORPORATIONInventors: ERIC J. LI, GUOTAO WANG, HUIYANG FEI, SAIRAM AGRAHARAM, OMKAR G. KARHADE, NITIN A. DESHPANDE
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Publication number: 20190157205Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: ApplicationFiled: January 22, 2019Publication date: May 23, 2019Applicant: INTEL CORPORATIONInventors: Nitin A. Deshpande, Omkar G. Karhade
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Publication number: 20190148268Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.Type: ApplicationFiled: December 20, 2018Publication date: May 16, 2019Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Rajendra C. DIAS, Edvin CETEGEN, Lars D. SKOGLUND
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Patent number: 10290561Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.Type: GrantFiled: September 28, 2016Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Edvin Cetegen, Omkar G. Karhade, Kedar Dhane, Chandra M. Jha
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Patent number: 10256198Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.Type: GrantFiled: March 23, 2017Date of Patent: April 9, 2019Assignee: INTEL CORPORATIONInventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
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Patent number: 10229882Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.Type: GrantFiled: August 3, 2017Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Nitin A. Deshpande, Omkar G. Karhade
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Patent number: 10192810Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.Type: GrantFiled: June 28, 2013Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund