Abstract: A Peripheral Component Interconnect express (PCIe) device includes a Direct Memory Access (DMA) device including a plurality of functions; and a PCIe interface device for performing communication between a host and the DMA device. The PCIe interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.

Abstract: A memory socket includes a frame having a base portion and a side portion, and a push-eject locking mechanism in physical communication with the base portion and with the side portion. The push-eject locking mechanism to transition between an unlocked position and a locked position. The push-eject locking mechanism includes an eject bar component and a lever component. The weight of the eject bar component biases the push-eject locking mechanism towards the unlocked position. Based on a force being exerted on the lever component, the lever component pivots and transition the push-eject locking mechanism from the unlocked position to the locked position.

Abstract: The FFT processor having an N-point Radix-4 multi-path delay commutator (R4MDC) structure having a power of 4 comprises: a first memory bank; and second to fourth memory banks configured to delay an output of data.

Abstract: A high-power single-wavelength semiconductor laser having multi-segment grating structure includes a cavity body, a gain layer, an electrode structure, a grating layer, an upper cladding layer, a lower cladding layer and a longitudinal waveguide structure. The cavity body has a resonant cavity, a reflective facet and an anti-reflective facet. The reflective and anti-reflective facets are respectively disposed to opposite first and second sides of the cavity body. The electrode structure is disposed on the resonant cavity. The grating layer in the resonant cavity includes a first sub-grating, a second sub-grating and no-corrugation segments, arranged in an alternate manner. The upper and lower cladding layers in the resonant cavity wrap the gain and grating layers to form a lateral waveguide structure. The longitudinal waveguide structure in the resonant cavity between the first side and the second side connects the first sub-grating, the second sub-grating and the no-corrugation segments.

Abstract: A learning processing device and method for pooling graph data of a hierarchical structure based on a grouping matrix, and a method for learning an artificial intelligence model. The learning processing device includes a memory and a processor in communication with the memory. The processor generates a grouping matrix of a secondary form, grouped based on a similarity of a pairwise nodes by inputting graph data into a pre-learned first artificial intelligence model; and decomposes the grouping matrix to generate a pooling matrix. The grouping matrix is decomposed in a square-root form to obtain a pooling operator.

Abstract: A coil electronic component includes a main body; a coil embedded in the main body, an insulating layer disposed on one surface of the main body, a first conductive layer covering a portion of the one surface, a second conductive layer covering another portion of the one surface, and first and external electrodes respectively covering the first conductive layer. The coil electronic component has a first length L1 in a first direction, and a second length L2 is a sum of a third length L3 in the first direction of a region where the insulating layer, the first conductive layer, and the first external electrode overlap and a fourth length L4 in the first direction of a region where the insulating layer, the second conductive layer, and the second external electrode overlap. A ratio L2/L1 is 0.3 or more and 0.7 or less.

Abstract: Disclosed herein is a multimedia device. The multimedia device includes: a display configured to display a user interface based on a pet care mode; and a controller configured to control the display. The controller is configured to: detect whether trigger conditions are satisfied, wherein the trigger conditions include selection by a user or absence of the user; and activate the pet care mode based on satisfaction of the trigger conditions.

Abstract: A multilayer capacitor may include a capacitor body including a dielectric layer and an internal electrode, and an external electrode disposed outside the capacitor body, where the capacitor body may include titanium (Ti) and indium (In), and in the entire capacitor body, the content of the indium (In) based on 100 moles of titanium (Ti) may be 0.2 moles to 4 moles.

Abstract: An electronic device including a panel and an actuator is disclosed. The panel includes a first substrate, a second substrate and a plurality of light-emitting elements. The second substrate is disposed on the first substrate, and the second substrate includes a plurality of main portions and a plurality of openings. The plurality of light-emitting elements are disposed on the plurality of main portions of the second substrate. The first substrate is disposed between the actuator and the second substrate. In a deformation mode, the panel is deformed by the actuator.

Abstract: The disclosed multilayer ceramic capacitor includes a ceramic main body including a first surface and a second surface facing in a first direction, a third surface and a fourth surface facing in a second direction and connecting the first surface and the second surface, and a fifth surface and a sixth surface facing in a third direction and connecting the first surface and the second surface, an internal electrode disposed inside the ceramic main body, a protective layer disposed on the third surface and the fourth surface of the ceramic main body, and a connection electrode covering the protective layer. The protective layer includes a first protective layer disposed on the third surface and a second protective layer disposed on the fourth surface, and has openings positioned on the third surface and the fourth surface.

Abstract: A touch detection circuit includes: a touch sensing unit including a plurality of driving electrodes and a plurality of sensing electrodes arranged to intersect the driving electrodes; first through n-th unique signal generators transmitting first through n-th unique signals, which have different voltage or current characteristics, to bodies of first through n-th users, respectively; at least one motion detection circuit detecting a touch direction and touch position of each of the first through n-th users; and a touch driving circuit driving the driving electrodes and the sensing electrodes to detect touch detection signals and generate touch position coordinate information, wherein the touch driving circuit selects any one user, of the first through n-th users, who performed a touch operation on the touch sensing unit according to a preset priority, and generates and outputs touch position coordinate information according to the touch position of the selected user.

Abstract: A method of fabricating a semiconductor device is provided. The method includes: providing an interlayer dielectric layer with a trench on a substrate in a first substrate processing apparatus in a vacuum state; forming a first metal barrier in the trench while the substrate is in the first substrate processing apparatus; unloading the substrate from the first substrate processing apparatus and exposing the substrate to a non-vacuum environment; providing the substrate in a second substrate processing apparatus of a vacuum state; forming a second metal barrier in the trench in the second substrate processing apparatus; and forming a metal pattern to fill the trench.

Abstract: An image presenting method and a display device are disclosed. The method includes: defining one vision region in a display interface of a foldable display via a first application programming interface; detecting a physical status of the foldable display; dividing the vision region into a first sub-vision region and a second sub-vision region in response to that the physical status of the foldable display is a folded status; and presenting a first desktop image and a second desktop image in the first sub-vision region and the second sub-vision region respectively via a second application programming interface, wherein one of the first desktop image and the second desktop image includes a toolbar image, and a presenting position of the toolbar image in the first sub-vision region or the second sub-vision region is variable.

Abstract: The present specification relates to a method of manufacturing a packaging substrate and a packaging substrate manufactured thereby. The packaging substrate according to the present specification includes a core layer including a glass substrate having a first surface and a second surface facing each other and a cavity portion passing through the glass substrate, wherein a cavity module is disposed in the cavity portion, the cavity module comprise a cavity element and a first insulating layer is formed on some surfaces other than one surface or on all the surface of the cavity element, and a second insulating layer is incorporated into the remaining portion of the cavity portion other than the cavity module, and the first insulating layer and the second insulating layer have different dielectric constants. Accordingly, an undulation phenomenon due to a gap between elements, a gap between the cavity portion and an element, and/or the like may be prevented, and a leakage current may be prevented from occurring.

Abstract: Provided is a system and method for migrating data. The method includes: receiving data, read count information about the data, and write count information about the data; selecting at least one memory block among a plurality of memory blocks based on a wear level of a plurality of memory blocks and the read count information and the write count information; and storing the data in the at least one memory block.

Abstract: A semiconductor package includes a buffer die, an intermediate core die stack on the buffer die, where the intermediate core die stack includes a plurality of intermediate core dies and a plurality of first gap filling portions that respectively overlap side surfaces of the plurality of intermediate core dies in a first direction, a top core die on the intermediate core die stack, and a second gap filling portion that overlaps side surfaces of the intermediate core die stack in the first direction and side surfaces of the top core die in the first direction.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: An electronic package is provided and includes: a thermally conductive chip; a circuit structure having a circuit layer; and an electronic component disposed between the circuit structure and the thermally conductive chip and electrically connected to the circuit layer, so as to dissipate the heat generated during the operation of the electronic component via the thermally conductive chip. A method of manufacturing the electronic package is further provided.

Abstract: A memory controller includes a scrub control circuit configured to generate a scrub command for instructing a scrub operation; and an address generation circuit configured to generate a scrub address having an address sequence in which a first column bit group of a column address, a row address, and a second column bit group of the column address are sequentially allocated from a least significant bit (LSB) to a most significant bit (MSB), and change a value of the scrub address according to the scrub command.

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface opposite to each other, a gate structure on the top surface of the substrate, a plurality of source/drain patterns on the top surface of the substrate and on opposite sides of the gate structure, a backside conductive line on the bottom surface of the substrate and electrically connected to at least one of the gate structure or a first source/drain pattern of the source/drain patterns, and a magnetic tunnel junction pattern electrically connected to a second source/drain pattern of the source/drain patterns.