Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: In a method for creating a group in a virtual environment, a first virtual object and a plurality of second virtual objects are displayed in the virtual environment. A touch input is received on at least one of the plurality of second virtual objects. Based on the at least one of the plurality of second virtual objects including at least two second virtual objects of the plurality of second virtual objects, the at least two second virtual objects from the plurality of second virtual objects are selected as group creation virtual objects. The group that includes the first virtual object and the group creation virtual objects is created. Apparatus and non-transitory computer-readable storage medium counterpart embodiments are also contemplated.

Abstract: A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.

Abstract: Systems and methods performed on a vehicle include: determining selected Internet of Things (IoT) devices from a plurality of IoT devices separate from the vehicle, wherein the selected IoT devices are selected based on being capable of performing a task including compute and/or storage for a vehicle subsystem; decomposing the task into a plurality of workloads to offboard for processing on respective selected IoT devices; and sending the workloads to the respective selected IoT devices.

Abstract: The present disclosure provides a display substrate, a preparing method thereof, and a display device. The display substrate includes: a base substrate including a spacing region; a plurality of light-emitting device groups on the base substrate, any two adjacent light-emitting device groups of the plurality of light-emitting device groups being spaced apart from each other by the spacing region; and a light-shielding layer on the base substrate. The light-shielding layer covers the plurality of light-emitting device groups and fills the spacing region, a first portion of the light-shielding layer covering the plurality of light-emitting device groups has a first thickness, a second portion of the light-shielding layer filling the spacing region has a second thickness, the first thickness is less than the second thickness.

Abstract: The present disclosure provides a method and an apparatus of resource adjustment for a service cluster, an electronic device and a storage medium. The method includes: determining resource adjustment information for the service cluster according to a task quantity of streaming data processing tasks to be processed; determining a core quantity to be adjusted corresponding to central processor units and the second quantity of computing nodes to be adjusted, according to the parallelism degree to be adjusted, the first quantity of the computing nodes that have been created in the service cluster, and a resource utilization rate of central processor units in each computing node that has been created; and executing the resource adjustment operation according to the core quantity to be adjusted and the second quantity, and obtaining a service cluster subject to resource adjusting.

Abstract: A mounting structure for mounting a data storage device includes a cage, a sliding piece, a door, and a lock. The cage has an opening and a cavity. The sliding piece is slidable between a first position and a second position. The sliding piece has a pushing part. The door is rotatably located on the sliding piece and configured for covering or uncovering the opening. The lock is located on the cage and configured for locking the door to cover the opening. When the data storage device is accommodated in the cavity, the door is locked by the lock and the sliding piece is located on the first position, when the lock unlocks the door and the sliding piece slides to the second position, the pushing part pushes the data storage device outwards from the cavity through the opening. A cabinet and a computing device are also disclosed.

Abstract: A processing system includes a first memory. The processing system is configured to obtain first data, where the first data is data to be written into the first memory; determine, based on first error distribution area information of at least one memory space included in the first memory, a first arrangement manner of a memory space occupied by a data symbol; determine the first data as M data symbols based on the first arrangement manner of the memory space occupied by the data symbol, where each of the M data symbols includes a plurality of data bits; perform first error correction code encoding on the M data symbols to obtain N first redundant symbols; and write the M data symbols and the N first redundant symbols into the first memory.

Abstract: The present application provides an insulation structure and an electronic device, where the insulation structure includes a first substrate, a first conductive body, and a first groove, the first substrate includes a first surface and a second surface oppositely disposed; the first conductive body is disposed on the first surface or second surface; the first groove is located on a same surface as the first conductive body and adjacent to the first conductive body; a surface of the first groove is provided with a first conductive layer, and the first conductive layer is electrically connected with the first conductive body. The insulation structure of the present application slows down the trend of potential line changes at the end of the first conductive body, reduces the electric field strength here, and improves the reliability of insulation.

Abstract: A single piece electrical connector for connecting two circuit elements incudes a housing and an interconnection member provided therein with an array of electrically conductive and elastic spring contact elements provided on the interconnection member to interconnect the two circuit elements electrically and mechanically in a stacked or coplanar configuration. In some embodiments, the single piece electrical connector connects to interconnection terminals of each circuit element by the application of a force normal to the surfaces of the circuit elements. In some embodiments, the housing of the connector is configured to apply and maintain the normal force between the elastic spring contact elements of the connector and the interconnection terminals of the circuit elements to form low resistance interconnections therebetween.

Abstract: A memory array includes a continuous active region extending along a direction. The memory array includes a first bit cell, which includes a first programming device and a pair of first reading devices defined on the continuous active region. The memory array includes a first programing word line coupled to a gate of the first programing device. The memory array includes a first reading word line coupled to gates of the pair of first reading devices. The memory array includes a bit line, wherein a first one of the pair of first reading devices is coupled between a first source/drain node of the first programing device and the bit line.

Abstract: An electronic package and a heat dissipation structure thereof are provided, in which supporting members of the heat dissipation structure are arranged in edge areas, and no supporting member is arranged in corner areas. In this way, the supporting members are interrupted at the corner areas, so that stress can be prevented from concentrating in the corner areas, and the entire electronic package can be prevented from warping and delamination.

Abstract: An image sensor includes a substrate. The image sensor includes a first photodiode (PD) having a first size in the substrate. The image sensor further includes a second PD having a second size in the substrate, wherein the first size is different from the second size. The image sensor further includes a first layer, wherein the first layer comprises a metal material or a dielectric material, and the first layer defines sidewalls of a first recess aligned with the first PD. The image sensor further includes a second layer in the first recess, wherein a portion of the first layer aligned with the second PD is free of the second layer, and the second layer overhangs the first layer.

Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.

Abstract: A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. The top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. The set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. The set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.

Abstract: The present disclosure relates to a solar cell, a sliced cell and a manufacturing method thereof, a photovoltaic module, and a photovoltaic system. The solar cell includes a substrate, a doped conductive layer, a third passivation film layer, and a second dielectric layer; the doped conductive layer and the second dielectric layer being sequentially stacked on a first surface of the substrate; the third passivation film layer being stacked on a second surface of the substrate; and the first surface and the second surface of the substrate being arranged opposite to each other; wherein the substrate further includes a plurality of first side surfaces adjacent between the first surface and the second surface; and the third passivation film layer further covers at least part of surfaces of the plurality of first side surfaces. The solar cell, the photovoltaic module, and the photovoltaic system in the present disclosure can reduce recombination losses at side edges of the solar cell and improve efficiency.

Abstract: A package includes a first package component; a second package component bonded to the first package component by a first plurality of solder connectors; and a first plurality of spacer connectors extending from the first package component to the second package component. A diameter of a spacer connector the first plurality of spacer connectors is larger than a height of a solder connector of the first plurality of solder connectors, and the first plurality of spacer connectors comprises a different material than the first plurality of solder connectors.