Abstract: A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

Abstract: A set of quantum controllers are operable to transmit quantum state data to a quantum control switch. The quantum control switch comprises vector processors that operate on the quantum state data from the set of quantum controllers. Each vector processor transmits a result of the operation to a corresponding quantum controller in the set of quantum controllers.

Abstract: A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

Abstract: In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

Abstract: Quantum algorithms are performed via a quantum computer, by generating a quantum control pulse in a quantum controller and transmitting the quantum control pulse to a quantum processor. The quantum control pulse interacts with a qubit in the quantum processor. Within the quantum controller, a pulse processor generates a plurality of raw pulses that are modified by a front end hardware module. During the normal operation of the quantum controller, samples of the raw and/or modified pulses may be selected and saved to memory. During a design for validation (DFV) mode, the proper operation of the quantum controller is determined according to a simulation of the quantum controller and the saved samples. The DFV mode may be performed in parallel with normal operation without affecting the resources of the quantum controller.

Abstract: In a quantum computer, quantum algorithms are performed by exciting a qubit with a quantum control pulse. This quantum control pulse is an electromagnetic RF signal that is generated at baseband according to an analog waveform. An application digitally generates samples of this analog waveform using multiple classical processors that control multiple physical channels in parallel.

Abstract: A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

Abstract: In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

Abstract: A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

Abstract: A system comprising a quantum control data exchange circuit that enables a large, variable number of pulse generation circuits to exchange data within the coherence time of a plurality of quantum elements to enable feedback-based quantum control of a large, variable number of quantum elements.

Abstract: A set of quantum controllers are operable to transmit quantum state data to a quantum control switch. The quantum control switch comprises vector processors that operate on the quantum state data from the set of quantum controllers. Each vector processor transmits a result of the operation to a corresponding quantum controller in the set of quantum controllers.

Abstract: A system comprising a quantum control data exchange circuit that enables a large, variable number of pulse generation circuits to exchange data within the coherence time of a plurality of quantum elements to enable feedback-based quantum control of a large, variable number of quantum elements.

Abstract: A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

Abstract: A distributed plurality of quantum controllers operate synchronously on shared data. The operations performed in each quantum controller may be non-deterministic and based on a dynamic instruction indication. The shared data may be based on results from all of the plurality of quantum controllers.

Abstract: A pulse generation circuit in a quantum controller operates synchronously with a pulse computation circuit. The pulse generation circuit generates a pulse associated with a quantum element operation. The pulse computation circuit is able to determine characteristics of a signal that is based on the pulse. These characteristics are used by the pulse generation circuit to modify the pulse.

Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

Abstract: Methods and systems for classical processing in a quantum controller are operable to receive data from a quantum processor and demodulate a feedback pulse according to a command, a vector of digital samples and a vector of quadrature reference inputs. The vector of digital samples correspond to a feedback pulse from the quantum processor at a first time, and the vector of quadrature reference inputs correspond to a phase and a frequency at a second time. Exemplary embodiments of the methods and systems for classical processing in the quantum controller are also operable to perform one or more ALU, CLU, Boolean and multiplication operations in parallel with demodulation.

Abstract: Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.

Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

Abstract: A compression circuit includes a buffer, a selection circuit, a compare circuit, and a control circuit. The buffer stores uncompressed data. The selection circuit generates a read pointer value to the buffer. The control circuit contains a programmable configuration register. The configuration register stores a depth value for reading uncompressed data from the history buffer. The control circuit generates control signals to the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value. Responsive to the second value corresponding to the depth value, the control circuit resets the read pointer value to the initial value. The compare circuit compares input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.