Patents by Inventor Oron Michael

Oron Michael has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10305470
    Abstract: In an aspect, the disclosure is directed to a circuit which includes not limited to a memory circuit which includes a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logical comparator circuit which is connected to the memory circuit and includes a first logical comparator which compares the first memory output voltage with a first power supply voltage to generate a first logical comparator output voltage and a second logical comparator which compares the second memory output voltage with a second power supply voltage to generate a second logical comparator output voltage; and a logical circuit which is electronically connected to the logical comparator circuit and receives a first logical comparator output voltage and a second logical comparator output voltage to perform a first logical operation which is used at least in part to generate a power on reset voltage.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Oron Michael, Dae Hyun Kim
  • Patent number: 10249346
    Abstract: A power supply includes a plurality of charge pump circuits. The charge pump circuits commonly generate an output voltage for programming a write data to the memory apparatus. Wherein, number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: April 2, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Oron Michael, Dae Hyun Kim
  • Publication number: 20190019539
    Abstract: A power supply includes a plurality of charge pump circuits. The charge pump circuits commonly generate an output voltage for programming a write data to the memory apparatus. Wherein, number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 17, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Oron Michael, Dae Hyun Kim
  • Patent number: 10170166
    Abstract: The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 1, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Oron Michael, Poongyeub Lee
  • Patent number: 10068654
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 4, 2018
    Assignee: Winbond Electronics Corporation
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Patent number: 9971647
    Abstract: The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 15, 2018
    Assignee: Winbond Electronics Corporation
    Inventor: Oron Michael
  • Publication number: 20170110196
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Inventors: Robin John JIGOUR, Hui CHEN, Oron Michael
  • Patent number: 9627082
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: April 18, 2017
    Assignee: Winbond Electronics Corporation
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Patent number: 9620231
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: April 11, 2017
    Assignee: Winbond Electronics Corporation
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Patent number: 9442798
    Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: September 13, 2016
    Assignee: Winbond Electronics Corporation
    Inventors: Oron Michael, Anil Gupta
  • Publication number: 20160189789
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: Winbond Electronics Corporation
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Publication number: 20160189788
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Patent number: 9367392
    Abstract: A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: June 14, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventor: Oron Michael
  • Patent number: 9324450
    Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 26, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Robin John Jigour, Hui Chen, Oron Michael
  • Publication number: 20160034351
    Abstract: The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Applicant: Winbond Electronics Corporation
    Inventor: Oron Michael
  • Publication number: 20160034352
    Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventors: Oron Michael, Anil Gupta
  • Publication number: 20160034346
    Abstract: A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 4, 2016
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventor: Oron Michael
  • Patent number: 9218888
    Abstract: A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 22, 2015
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuki Yamauchi, Katsutoshi Suito, Oron Michael, Jongjun Kim, Youn-Cherl Shin
  • Patent number: 9128822
    Abstract: Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: September 8, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Oron Michael, Robin John Jigour, Anil Gupta
  • Patent number: 9082499
    Abstract: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: July 14, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventor: Oron Michael