Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

Abstract: In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

Abstract: In an aspect, the disclosure is directed to a circuit which includes not limited to a memory circuit which includes a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logical comparator circuit which is connected to the memory circuit and includes a first logical comparator which compares the first memory output voltage with a first power supply voltage to generate a first logical comparator output voltage and a second logical comparator which compares the second memory output voltage with a second power supply voltage to generate a second logical comparator output voltage; and a logical circuit which is electronically connected to the logical comparator circuit and receives a first logical comparator output voltage and a second logical comparator output voltage to perform a first logical operation which is used at least in part to generate a power on reset voltage.

Abstract: A power supply includes a plurality of charge pump circuits. The charge pump circuits commonly generate an output voltage for programming a write data to the memory apparatus. Wherein, number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.

Abstract: A power supply includes a plurality of charge pump circuits. The charge pump circuits commonly generate an output voltage for programming a write data to the memory apparatus. Wherein, number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.

Abstract: The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.

Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.