Abstract: A continuous read operation may be achieved by using a data buffer having a partitioned data register and a partitioned cache register, user configurable internal ECC associated with the cache register, and fast bad block management. During a data read operation, the ECC status may be indicated by ECC status bits. The status (1:1), for example, may indicate for the Continuous Read Mode that the entire data output contains more than 4 bits errors/page in multiple pages. However, one may wish to know the ECC status of each page or of each page partition. For the former, the ECC status for the entire page may be determined and made in the status register at the end of the output of the page. For the latter, the ECC status of each page partition may be determined and output before output of the corresponding page partition.

Abstract: A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.

Abstract: Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.

Abstract: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.

Abstract: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.

Abstract: A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.

Abstract: A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.

Abstract: Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.

Abstract: A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.

Abstract: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.

Abstract: A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations.

Abstract: A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations.

Abstract: Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current.