Abstract: A method useful for network and spectrum defense which operates to analyze cyber data and spectra while performing real time optimization which is based on the analyzed cyber data or spectrum. The method utilizes quantum computing and reconfigurable qubits with built-in memory to sample a target cyber data or spectrum, search through the sample and determine a desired or required network or spectrum reallocation, and determine optimal values for its order parameters and Hamiltonian and tune the qubits in accordance with the determination. An embodiment may provide for spectrum optimization that minimizes frequency bandwidth, power, and bit error rate. The desired or required network or spectrum reallocation and optimal values order parameters and Hamiltonian may be stored in the built-in memory to facilitate machine learning.

Abstract: A method useful for network and spectrum defense which operates to analyze cyber data and spectra while performing real time optimization which is based on the analyzed cyber data or spectrum. The method utilizes quantum computing and reconfigurable qubits with built-in memory to sample a target cyber data or spectrum, search through the sample and determine a desired or required network or spectrum reallocation, and determine optimal values for its order parameters and Hamiltonian and tune the qubits in accordance with the determination. An embodiment may provide for spectrum optimization that minimizes frequency bandwidth, power, and bit error rate. The desired or required network or spectrum reallocation and optimal values order parameters and Hamiltonian may be stored in the built-in memory to facilitate machine learning.

Abstract: A multifunctional quantum node device involving a semiconductor vacancy qubit structure, a superconductor quantum memory nanowire coupled with a spin state of the semiconductor vacancy qubit structure, and a superconductor qubit logic circuit coupled with the superconductor quantum memory nanowire and the semiconductor vacancy qubit structure, whereby the device is a hybrid device operable as an interface for at least one of computing and quantum-entangled networking.

Abstract: A device includes a plurality of optoelectronic gates. Each gate includes a nanowire, and a topological insulator coating the nanowire. The topological insulator is configured to isolate entanglement action of a nanoparticle in the nanowire, and an ion is coupled to the nanoparticle in the nanowire when the ion is photoactive.

Abstract: A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.

Abstract: A tunable quantum qubit circuit comprising: a plurality of interconnected Josephson tunneling junctions sculpted in-situ on-chip, wherein each Josephson tunneling junction comprises a pair of high temperature superconductors separated by an active region having a controlled charge density; a capacitive-coupled control gate operatively coupled to the Josephson tunneling junctions and configured to simultaneously modulate energy levels of the Josephson tunneling junctions; and independent control gates operatively coupled to the Josephson tunneling junctions, wherein the independent control gates are reconfigurable on-the-fly by an operator.

Abstract: A process for constructing a superconducting Josephson-based nonvolatile quantum memory device comprising: sequentially depositing on a silicon substrate a thermal oxide buffer layer, a superconductor bottom-electrode thin film, and an oxide isolation layer; patterning an active window having dimensions smaller that 10 nanometers in the oxide isolation layer; then sequentially depositing a bottom tunnel oxide layer, a charge-trapping layer, a top cap, and a top superconductor electrode layer; defining an active region by dry etching down to the oxide isolation layer while protecting the active region from etch chemistry; depositing a device passivation layer; defining and patterning vias from a top of the device passivation layer to the superconductor bottom-electrode thin film and to the top superconductor electrode of the active region; and depositing metal interconnect into the vias.

Abstract: A voltage controlled oscillator comprising a substrate and a bilayer graphene transistor formed on the substrate. The transistor has two signal terminals and a gate terminal positioned in between the signal terminals. A voltage controlled PZT or MEMS capacitor is also formed on the substrate. The capacitor is electrically connected to the transistor gate terminal. At least one component is connected to the transistor and capacitor to form a resonant circuit.

Abstract: Electronic devices and methods of forming an electronic device are disclosed herein. An electronic device may include a first 2D atomic crystal layer; a second 2D atomic crystal layer disposed atop the first 2D atomic crystal layer; and an interface comprising van-der-Waals bonds between the first 2D atomic crystal layer and the second 2D atomic crystal layer. A method of forming an electronic device may include depositing a first 2D atomic crystal layer; and depositing a second 2D atomic crystal layer atop the first 2D atomic crystal layer; wherein an interface is formed between the first 2D atomic crystal layer and the second 2D atomic crystal layer via van-der-Waals bonding.

Abstract: A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.

Abstract: Embodiments of graphene channel transistors and methods for producing same are provided herein. In some embodiments, a graphene channel transistor may include a substrate a having a source region, a drain region, and a dielectric material disposed between the source and drain regions; a channel region comprising a graphene layer disposed atop the dielectric material and partially atop the source and drain regions; and a composite gate electrode comprising an insulator layer disposed atop the graphene layer and a conductive layer disposed atop the insulator layer.

Abstract: A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.

Abstract: A voltage controlled oscillator comprising a substrate and a bilayer graphene transistor formed on the substrate. The transistor has two signal terminals and a gate terminal positioned in between the signal terminals. A voltage controlled PZT or MEMS capacitor is also formed on the substrate. The capacitor is electrically connected to the transistor gate terminal. At least one component is connected to the transistor and capacitor to form a resonant circuit.

Abstract: A UV detector has a UV detection thin film of coated spherical silicon nanoparticles formed upon a substrate. The detector includes structures to bias the thin film. In preferred embodiments, a thin conductor that is at least semi-transparent to UV radiation is formed over the thin film. In preferred embodiments, the UV detector is formed as a silicon based integration, upon a device quality silicon wafer.

Abstract: A UV detector has a UV detection thin film of coated spherical silicon nanoparticles formed upon a substrate. The detector includes structures to bias the thin film. In preferred embodiments, a thin conductor that is at least semi-transparent to UV radiation is formed over the thin film. In preferred embodiments, the UV detector is formed as a silicon based integration, upon a device quality silicon wafer.