Patents by Inventor Osamu Aizawa
Osamu Aizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220078946Abstract: An information processing device includes: a first distributing layer distributer configured to distribute a coolant for cooling electronic devices; and a second distributing layer distributer coupled to the first distributing layer distributer and configured to distribute the coolant, wherein the first distributing layer distributer includes a first distributing pipe and first distributing connecting pipes branched from the first distributing pipe, the first distributing pipe is disposed so that an axis of the first distributing pipe is parallel with the height direction, and the first distributing connecting pipes are arranged in the height direction, wherein the second distributing layer distributer includes second distributing pipes which are coupled to the respective first distributing connecting pipes, each of the second distributing pipes is disposed so that an axis of the second distributing pipe is parallel with the height direction, and the second distributing pipes are arranged in the height directType: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Applicant: FUJITSU LIMITEDInventors: Koji NAKAGAWA, Nobumitsu Aoki, Osamu Aizawa, Keita Hirai, Tsuyoshi So
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Patent number: 10701834Abstract: An information processing apparatus includes a plurality of electronic apparatus stacked over a plurality of hierarchies in the information processing apparatus, a heat exchanger that cools refrigerant liquid for cooling the plurality of electronic apparatus, a first distributor that distributes the refrigerant liquid from the heat exchanger to the plurality of hierarchies, a plurality of second distributor that stores the refrigerant liquid temporarily, and a plurality of pipes that branched from the distribution pipes to the plurality of the electronic apparatus, wherein the number of the second distributor increases toward a hierarchy on downstream side, the pipes of the last hierarchy are coupled to the electronic apparatus.Type: GrantFiled: September 24, 2018Date of Patent: June 30, 2020Assignee: FUJITSU LIMITEDInventors: Tsuyoshi So, Osamu Aizawa, Nobumitsu Aoki, Koji Nakagawa, Keita Hirai
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Patent number: 10342164Abstract: A rack mount-type information processing apparatus includes: a plurality of slots, into each of which an electronic device is inserted, a liquid-cooled element provided in a cooling target included in the electronic device, a liquid to cool the cooling target being circulated in the liquid-cooled element; a manifold pipe extending in a direction where the slots are arranged; and a plurality of connection pipes configured to interconnect the liquid-cooled element and the manifold pipe, and coupled in parallel to the manifold pipe at a portion of the manifold pipe which corresponds to at least one slot among the plurality of slots.Type: GrantFiled: October 5, 2017Date of Patent: July 2, 2019Assignee: FUJITSU LIMITEDInventors: Tsuyoshi So, Osamu Aizawa, Keita Hirai, Koji Nakagawa, Yoshinori Uzuka, Nobumitsu Aoki, Naofumi Kosugi
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Publication number: 20190104646Abstract: An information processing apparatus includes a plurality of electronic apparatus stacked over a plurality of hierarchies in the information processing apparatus, a heat exchanger that cools refrigerant liquid for cooling the plurality of electronic apparatus, a first distributor that distributes the refrigerant liquid from the heat exchanger to the plurality of hierarchies, a plurality of second distributor that stores the refrigerant liquid temporarily, and a plurality of pipes that branched from the distribution pipes to the plurality of the electronic apparatus, wherein the number of the second distributor increases toward a hierarchy on downstream side, the pipes of the last hierarchy are coupled to the electronic apparatus.Type: ApplicationFiled: September 24, 2018Publication date: April 4, 2019Applicant: FUJITSU LIMITEDInventors: Tsuyoshi So, Osamu Aizawa, Nobumitsu Aoki, Koji NAKAGAWA, Keita Hirai
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Publication number: 20180177079Abstract: An information processing device includes: a first distributing layer distributer configured to distribute a coolant for cooling electronic devices; and a second distributing layer distributer coupled to the first distributing layer distributer and configured to distribute the coolant, wherein the first distributing layer distributer includes a first distributing pipe and first distributing connecting pipes branched from the first distributing pipe, the first distributing pipe is disposed so that an axis of the first distributing pipe is parallel with the height direction, and the first distributing connecting pipes are arranged in the height direction, wherein the second distributing layer distributer includes second distributing pipes which are coupled to the respective first distributing connecting pipes, each of the second distributing pipes is disposed so that an axis of the second distributing pipe is parallel with the height direction, and the second distributing pipes are arranged in the height directType: ApplicationFiled: December 6, 2017Publication date: June 21, 2018Applicant: FUJITSU LIMITEDInventors: Koji Nakagawa, Nobumitsu Aoki, Osamu Aizawa, Keita Hirai, Tsuyoshi So
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Publication number: 20180132387Abstract: A rack mount-type information processing apparatus includes: a plurality of slots, into each of which an electronic device is inserted, a liquid-cooled element provided in a cooling target included in the electronic device, a liquid to cool the cooling target being circulated in the liquid-cooled element; a manifold pipe extending in a direction where the slots are arranged; and a plurality of connection pipes configured to interconnect the liquid-cooled element and the manifold pipe, and coupled in parallel to the manifold pipe at a portion of the manifold pipe which corresponds to at least one slot among the plurality of slots.Type: ApplicationFiled: October 5, 2017Publication date: May 10, 2018Applicant: FUJITSU LIMITEDInventors: Tsuyoshi So, Osamu Aizawa, Keita Hirai, Koji NAKAGAWA, Yoshinori Uzuka, Nobumitsu Aoki, NAOFUMI KOSUGI
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Patent number: 9951999Abstract: A cooling device includes: a refrigerant circulation loop configured to depressurizing the inside thereof, the refrigerant circulation loop includes, an evaporator that vaporizes a part of refrigerant by heat generated by an electronic component, a condenser that cools the refrigerant, and a pump that circulates the refrigerant, wherein a filling ratio of liquid refrigerant to a volume of the refrigerant circulation loop is configured to maintain a refrigerant circulation capability of the pump.Type: GrantFiled: December 16, 2014Date of Patent: April 24, 2018Assignee: FUJITSU LIMITEDInventors: Tsuyoshi So, Hideo Kubo, Osamu Aizawa, Nobuyuki Hayashi, Teru Nakanishi, Yoshinori Uzuka, Nobumitsu Aoki
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Patent number: 9620435Abstract: An evaporator includes a housing in which an evaporator chamber configured to evaporate a refrigerant is formed; a heat transfer surface provided on an inner wall of the housing and having a hot area which is a part that becomes hot due to heat transferred from a heating element to the housing; and a supply port formed in the housing, opposed to the hot area and configured to eject the refrigerant supplied from a supply pipe to the hot area, wherein a narrow groove is formed in the heat transfer surface.Type: GrantFiled: April 28, 2015Date of Patent: April 11, 2017Assignee: FUJITSU LIMITEDInventors: Atsushi Endo, Osamu Aizawa, Hideo Kubo
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Publication number: 20150334876Abstract: An evaporator includes a housing in which an evaporator chamber configured to evaporate a refrigerant is formed; a heat transfer surface provided on an inner wall of the housing and having a hot area which is a part that becomes hot due to heat transferred from a heating element to the housing; and a supply port formed in the housing, opposed to the hot area and configured to eject the refrigerant supplied from a supply pipe to the hot area, wherein a narrow groove is formed in the heat transfer surface.Type: ApplicationFiled: April 28, 2015Publication date: November 19, 2015Inventors: Atsushi Endo, Osamu Aizawa, Hideo Kubo
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Publication number: 20150184949Abstract: A cooling device includes: an evaporator that vaporizes a part of a refrigerant by heat generated by an electronic component; a condenser that cools the refrigerant; a refrigerant circulation loop coupled to the evaporator and the condenser, an inside of the refrigerant circulation loop is depressurized; and a pump that circulates the refrigerant, wherein a filling ratio of the liquid refrigerant to a volume of the refrigerant circulation loop is 50% or more.Type: ApplicationFiled: December 16, 2014Publication date: July 2, 2015Inventors: Tsuyoshi So, Hideo Kubo, Osamu Aizawa, Nobuyuki HAYASHI, TERU NAKANISHI, Yoshinori Uzuka, Nobumitsu Aoki
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Publication number: 20150062827Abstract: A heat sink includes: a fixing unit fixed to a heating element; and a heat dissipation unit including a heat dissipation protruding portion and configured to slide with respect to the fixing unit.Type: ApplicationFiled: July 9, 2014Publication date: March 5, 2015Inventors: Osamu Aizawa, Tsuyoshi So, Eiji Makabe, Yoshinori Uzuka
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Patent number: 8264850Abstract: An electronic device package includes an electronic device including a plurality of input/output terminals, a wiring board which places the electronic device on a first surface and includes wiring connected to the input/output terminals of the electronic device, and a first connection terminal formed on a second surface of the wiring board and connected to the wiring, wherein the first connection terminal has an uneven contact surface formed to receive solder material placed thereon.Type: GrantFiled: March 30, 2009Date of Patent: September 11, 2012Assignee: Fujitsu LimitedInventors: Tsuyoshi So, Hideki Maeda, Osamu Aizawa, Hideo Kubo
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Patent number: 7872875Abstract: An electronic part having mounting terminals made of a thermally-meltable bonding material is mounted on a mounting board. A structural part is used for moving a height-adjusting member to a position under the electronic part in a process of heating and melting the thermally-meltable bonding material so as to maintain a predetermined distance between the electronic part and the mounting board.Type: GrantFiled: October 4, 2007Date of Patent: January 18, 2011Assignee: Fujitsu LimitedInventors: Tsuyoshi So, Yoshinori Uzuka, Osamu Aizawa, Hideo Kubo
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Publication number: 20090242258Abstract: An electronic device package includes an electronic device including a plurality of input/output terminals, a wiring board which places the electronic device on a first surface and includes wiring connected to the input/output terminals of the electronic device, and a first connection terminal formed on a second surface of the wiring board and connected to the wiring, wherein the first connection terminal has an uneven contact surface formed to receive solder material placed thereon.Type: ApplicationFiled: March 30, 2009Publication date: October 1, 2009Applicant: FUJITSU LIMITEDInventors: Tsuyoshi So, Hideki Maeda, Osamu Aizawa, Hideo Kubo
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Publication number: 20080158843Abstract: An electronic part having mounting terminals made of a thermally-meltable bonding material is mounted on a mounting board. A structural part is used for moving a height-adjusting member to a position under the electronic part in a process of heating and melting the thermally-meltable bonding material so as to maintain a predetermined distance between the electronic part and the mounting board.Type: ApplicationFiled: October 4, 2007Publication date: July 3, 2008Applicant: FUJITSU LIMITEDInventors: Tsuyoshi SO, Yoshinori UZUKA, Osamu AIZAWA, Hideo KUBO
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Patent number: 7280373Abstract: A printed board unit includes a mother board 60, and a first board unit 70-1 and a second board unit 70-2 that face each other and are vertically mounted onto the mother board 60 with connector devices 100-1 and 100-2. The first board unit 70-1 has memory mounting boards 81-1 horizontally mounted to a region near the lower end of a vertically standing daughter board 71-1. The second board unit 70-2 has memory mounting boards 81-2 horizontally mounted to a region near the upper end of a vertically standing daughter board 71-2. The memory mounting boards 81-1 of the first board unit 70-1 are arranged on the lower side, while the memory mounting boards 81-2 of the second board unit 70-2 are arranged on the upper side.Type: GrantFiled: February 19, 2004Date of Patent: October 9, 2007Assignee: Fujitsu LimitedInventor: Osamu Aizawa
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Publication number: 20070178645Abstract: The present invention provides a method for manufacturing semiconductor device. An element isolation structural portion is formed in a semiconductor substrate, an element isolation gate insulating film is deposited, a floating gate film is deposited, a spacer film is deposited, and an etching resistant mask pattern is formed on the spacer film. Then, isotropic etching using the etching resistant mask pattern as a mask is performed to remove the spacer film lying in an area broader than an area exposed from the etching resistant mask pattern, which extends from an end edge portion of the etching resistant mask pattern to a lower surface of the etching resistant mask pattern to thereby form a spacer film pattern. Further, anisotropic etching using the etching resistant mask pattern as a mask is performed to remove the floating gate film thereby forming, at an upper end portion, a floating gate having an upper end surface portion placed at an obtuse angle to an exposed end surface.Type: ApplicationFiled: July 26, 2006Publication date: August 2, 2007Inventor: Osamu Aizawa
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Patent number: 7167374Abstract: A circuit substrate comprises a first substrate on a first surface of which circuit elements are loaded, a second substrate on which the first substrate is loaded, and noise reduction elements. Each of the noise reduction elements is sandwiched between an area of a second surface of the first substrate over against the first surface of the first substrate and a surface of the second substrate facing the second surface of the first substrate. The noise reduction element is connected between a power source terminal of the second surface of the first substrate and a power source terminal of the surface of the second substrate, and/or between a ground terminal of the second surface of the first substrate and a ground terminal of the surface of the second substrate.Type: GrantFiled: September 24, 2003Date of Patent: January 23, 2007Assignee: Fujitsu LimitedInventor: Osamu Aizawa
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Patent number: 6881676Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate electrodes on a semiconductor substrate, forming an etching prevention film over the surface of the adjacent gate electrodes and on the semiconductor substrate between the adjacent gate electrodes, and forming an organic insulation film having heat-resistance on the etching prevention film. The method further includes removing the organic insulation film above the gate electrodes in such a manner that the organic insulation film remains between the gate electrodes, forming an interlayer insulation film on a laminate section obtained by the organic insulation film removing step, forming a contact hole by removing the interlayer insulation film on the remaining organic insulation film with a width wider than the distance between the gate electrodes, and exposing the semiconductor substrate between the gate electrodes by removing the organic insulation film and the etching prevention film remaining inside the contact hole.Type: GrantFiled: November 1, 2002Date of Patent: April 19, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Osamu Aizawa
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Publication number: 20040188815Abstract: A circuit substrate comprises a first substrate on a first surface of which circuit elements are loaded, a second substrate on which the first substrate is loaded, and noise reduction elements. Each of the noise reduction elements is sandwiched between an area of a second surface of the first substrate over against the first surface of the first substrate and a surface of the second substrate facing the second surface of the first substrate. The noise reduction element is connected between a power source terminal of the second surface of the first substrate and a power source terminal of the surface of the second substrate, and/or between a ground terminal of the second surface of the first substrate and a ground terminal of the surface of the second substrate.Type: ApplicationFiled: September 24, 2003Publication date: September 30, 2004Inventor: Osamu Aizawa