Abstract: An electrooptical device includes a first substrate, a first electrode disposed on the first substrate, a second substrate facing the first substrate, a second electrode disposed on the second substrate, and a liquid crystal layer positioned between the first substrate and the second substrate. The first substrate includes a first terminal, a second terminal, a first conductive portion electrically coupled to the first terminal, and a second conductive portion electrically coupled to the second terminal, the second substrate includes a third conductive portion electrically coupled to the second electrode, and a fourth conductive portion electrically coupled to the third conductive portion, and the electrooptical device further includes a first coupling member electrically coupling the first conductive portion and the third conductive portion, and a second coupling member electrically coupling the second conductive portion and the fourth conductive portion.

Abstract: According to one embodiment, a complementary and latching sense amplifier circuit includes a sense amplifier main unit that receives an input signal input from each of a pair of input terminals to a corresponding gate terminal. The sense amplifier circuit includes: separation gates configured to electrically disconnect the input terminals and the corresponding respective gate terminals from each other before the sense amplifier main unit is effectively put into an enabled state; and capacitive elements having a same capacitance, each of the capacitive elements being connected between the corresponding gate terminal and a power supply.

Abstract: A sense timing generation circuit of an embodiment is a sense timing generation circuit that outputs, from an output terminal, a sense amplifier enable signal for bringing a sense amplifier into an enable state, based on a clock signal input from an input terminal, and includes a delay circuit unit that has a temperature characteristics by which a delay amount decreases in accordance with a temperature rise, includes a plurality of types of a plurality of delay circuits being different in the temperature characteristics, and delays the clock signal and outputs the clock signal as the sense amplifier enable signal, and a connection switch unit that switches a connection state of a plurality of delay circuits in the delay circuit unit from the input terminal to the output terminal.

Abstract: A reference voltage generating circuit according to an embodiment includes: an original reference voltage generating unit that generates an original reference voltage; and a reference voltage correcting unit that decreases the original reference voltage as the temperature rises and outputs the original reference voltage as a reference voltage to a sense amplifier, and thus it is possible to perform highly reliable operation while the influence of the temperature is reduced.

Abstract: According to one embodiment, a semiconductor memory device includes an SRAM. The SRAM comprises a memory cell including a first inverter, a second inverter, a first transfer transistor, and a second transfer transistor and a peripheral circuit configured to supply various voltages to a word line, a first bit line, and a second bit line. Each transistor of the memory cell is formed by a high-withstand-voltage transistor, and each transistor of the peripheral circuit is formed by a low-withstand-voltage transistor.

Abstract: According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.

Abstract: According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.

Abstract: A rectangular tube (10) of a terminal fitting (T) includes a lid plate (16) extending substantially at a right angle from the extending end of a right side plate (15) and formed with a locking hole (20) extending over the entire width. A front plate (19F) is cantilevered from the right side plate (15) and arranged before the locking hole (20). A rear plate (19R) is cantilevered from the right side plate independently of the front plate (19F) and is behind and adjacent to the locking hole (20). A retracted portion (21) is formed over the entire width at the rear plate (19R), retracted inwardly of the rectangular tube (10) from the front plate (19F) to provide a height difference within the range of an engagement margin with a locking projection (34) and capable of facing a rear end of the locking projection (34).

Abstract: A terminal fitting (10) includes a tubular main portion (11) into which a mating male tab (91) is insertable. A resiliently deformable contact piece (22) which is to be resiliently held in contact with the male tab 91 is formed in the main portion (11), and a contact portion (32) which receives the male tab (91) is formed fixedly at a position facing the resilient contact piece (22). A ceiling wall (19) is at a position opposite to the resilient contact piece outward of the contact portion (32). A ceiling wall lance hole (27) penetrates through the ceiling wall (19) and can receive a locking lance (64) for retaining the terminal fitting (10) in a connector (60). A clearance (33) is formed between the ceiling wall (19) and the contact portion (32) for allowing the entry of the locking lance (54).

Abstract: A terminal fitting (T) includes a locking plate (19) extending from a first side plate (17) and a stabilizer (22) projecting from a second side plate (18). A cutout (35) is formed at the extending end edge of the locking plate (19) and engages the stabilizer (22) to restrict relative displacements of the locking plate (19) and the second side plate (18) to define a first linking portion (27) that links the base plate (16) and a first contact piece (23). A second linking portion (28) links the second side plate (18) and a second contact piece (24). A restricting portion (36) is formed on the locking plate (19) and restricts displacement of the second contact piece (24) away from the first plate-like contact piece (23).

Abstract: A terminal fitting (10) includes a tubular main portion (11) into which a mating male tab (91) is insertable from the front. A resilient contact piece (22) which is to be resiliently held in contact with the male tab (91) is resiliently deformably formed in the main portion (11), and a contact portion (32) which receives the male tab (91) is fixedly formed at a position facing the resilient contact piece (22). The contact portion (32) includes a folded part formed by folding a backward extending part of an outer wall of the main portion (11) inwardly and forwardly. A curved R surface (41) is formed on the outer surface of the folded part of the contact portion (32).

Abstract: A semiconductor storage device according to an embodiment includes: a memory cell in which data is stored; a word line through which the memory cell is selected in each row; a bit line through which a signal read from the memory cell is transmitted in each column; a speed detector that detects a read speed of the memory cell; and a voltage controller that controls at least one of a voltage at the word line and a cell power supply voltage of the memory cell based on the read speed of the memory cell.

Abstract: According to an embodiment, provided are a memory cell configured to store data, a word line configured to select the memory cell in each row, a bit line configured to transfer a signal read from a memory cell in each column, a self-test circuit configured to test an operation of the memory cell, and a regulator configured to set a voltage of the word line or a cell power supply voltage of the memory cell to accelerate a disturb failure of the memory cell, based on an acceleration command from the self-test circuit.

Abstract: A terminal fitting (T) includes a locking plate (19) extending from a first side plate (17) and a stabilizer (22) projecting from a second side plate (18). A cutout (35) is formed at the extending end edge of the locking plate (19) and engages the stabilizer (22) to restrict relative displacements of the locking plate (19) and the second side plate (18) to define a first linking portion (27) that links the base plate (16) and a first contact piece (23). A second linking portion (28) links the second side plate (18) and a second contact piece (24). A restricting portion (36) is formed on the locking plate (19) and restricts displacement of the second contact piece (24) away from the first plate-like contact piece (23).

Abstract: A rectangular tube (10) of a terminal fitting (T) includes a lid plate (16) extending substantially at a right angle from the extending end of a right side plate (15) and formed with a locking hole (20) extending over the entire width. A front plate (19F) is cantilevered from the right side plate (15) and arranged before the locking hole (20). A rear plate (19R) is cantilevered from the right side plate independently of the front plate (19F) and is behind and adjacent to the locking hole (20). A retracted portion (21) is formed over the entire width at the rear plate (19R), retracted inwardly of the rectangular tube (10) from the front plate (19F) to provide a height difference within the range of an engagement margin with a locking projection (34) and capable of facing a rear end of the locking projection (34).

Abstract: A terminal fitting (10) includes a tubular main portion (11) into which a mating male tab (91) is insertable. A resiliently deformable contact piece (22) which is to be resiliently held in contact with the male tab 91 is formed in the main portion (11), and a contact portion (32) which receives the male tab (91) is formed fixedly at a position facing the resilient contact piece (22). A ceiling wall (19) is at a position opposite to the resilient contact piece outward of the contact portion (32). A ceiling wall lance hole (27) penetrates through the ceiling wall (19) and can receive a locking lance (64) for retaining the terminal fitting (10) in a connector (60). A clearance (33) is formed between the ceiling wall (19) and the contact portion (32) for allowing the entry of the locking lance (54).

Abstract: A terminal fitting (10) includes a tubular main portion (11) into which a mating male tab (91) is insertable from the front. A resilient contact piece (22) which is to be resiliently held in contact with the male tab (91) is resiliently deformably formed in the main portion (11), and a contact portion (32) which receives the male tab (91) is fixedly formed at a position facing the resilient contact piece (22). The contact portion (32) includes a folded part formed by folding a backward extending part of an outer wall of the main portion (11) inwardly and forwardly. A curved R surface (41) is formed on the outer surface of the folded part of the contact portion (32).

Abstract: According to one embodiment, in a memory cell array, a plurality of memory cells is arranged in an array. A read circuit reads out data from the memory cells. A word line driver drives a word line of the memory cells. A characteristic control unit controls a specific characteristic of the memory cells. A word-line-potential adjusting unit adjusts a potential of the word line based on a distribution of the characteristic when the specific characteristic of the memory cells is controlled.

Abstract: A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.

Abstract: According to one embodiment, a read bit line is driven based on data read out from a memory cell. A read port drives the read bit line based on data stored in a storage node. A read word line performs row selection via the read port at a time of reading from the memory cell. A coupling driver assists a write operation to the memory cell by controlling a potential of the storage node via the read port.