Abstract: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Abstract: A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor device includes a memory cell array having SRAM cells arranged in an array form, word lines connected to the SRAM cells for respective rows, a row decoder which selects the word lines one by one during normal operation and multi-select word lines which are not adjacent to each other during low-voltage operation, a load circuit which sets the level of the selected word line to potential lower than power supply voltage, and a controller which controls the row decoder and load circuit to selectively control selection of the word lines and the load circuit.

Abstract: A semiconductor device includes a device isolation insulating film which is provided in a semiconductor substrate, and an insulated-gate field-effect transistor which is disposed adjacent to the device isolation insulating film in a gate length direction, the insulated-gate field-effect transistor including a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a pair of impurity diffusion layers which are provided spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode, and a redundant impurity diffusion layer which is provided between the device isolation insulating film and one of the pair of impurity diffusion layers.

Abstract: A board connector (1) has a housing (10) and terminal fittings (20) penetrate through the back wall (11) of the housing (10). A board connecting portion (21) of each terminal fitting (20) penetrates through the back wall (11) and is solder-connected to a board (2). The housing (10) has a heat transfer inhibiting portion for inhibiting heat transfer to the back wall (11). The heat transfer inhibiting portion has a through-hole (13) or heat-insulating grooves (17) in the back wall (11). As a result, heat transfer to the back wall (11) is inhibited and deformation of the back wall (11) due to thermal expansion also is inhibited. Consequently, it is possible to prevent the terminal fittings (20) from separating from the board (2) and going into a state of being not solder-connected thereto.

Abstract: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.

Abstract: Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.

Abstract: A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern required to test the data memory, and which generates, from the test pattern, code information having an error checking function, and outputs the code information to the code memory as the ECC code.

Abstract: A semiconductor memory device operates using a first power supply and a second power supply. The device includes a static memory cell which receives the first power supply, a word line which is connected to the memory cell, and a decoder which controls selection/deselection of the word line on the basis of an address signal having a voltage of the second power supply. The decoder includes a level shifter which changes a voltage of the word line to a voltage of the first power supply, and a switching circuit which receives the first power supply and applies a voltage lower than the first power supply to the level shifter in selecting the word line.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a source terminal which supplies a source potential to the memory cells, a first switching element which electrically connects the source terminal and a first power supply potential in an operation mode of the memory cells, and electrically disconnects the source terminal and the first power supply potential in a standby mode of the memory cells, a clamp MIS transistor which is series-connected between the source terminal and the first power supply potential, and clamps the source potential in the standby mode, a bias generation circuit which supplies a first bias potential to a gate terminal of the clamp MIS transistor, and a switching circuit which switches a potential of a back gate terminal of the clamp MIS transistor between a test mode and a non-test mode.

Abstract: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

Abstract: A semiconductor device whose operation frequency and power supply voltage are dynamically controlled according to a load subjected to a process to be performed is disclosed. The semiconductor device includes a memory cell array having SRAM cells arranged in an array form, word lines connected to the SRAM cells for respective rows, a row decoder which selects the word lines one by one during normal operation and multi-select word lines which are not adjacent to each other during low-voltage operation, a load circuit which sets the level of the selected word line to potential lower than power supply voltage, and a controller which controls the row decoder and load circuit to selectively control selection of the word lines and the load circuit.

Abstract: A semiconductor memory device includes a first inverter circuit and a second inverter circuit, a first transfer gate which is connected between a first power node of the first inverter circuit and a first bit line, a second transfer gate which is connected between a second power node of the second inverter circuit and a second bit line, a first word line connected to gate terminals of the first transfer gate and the second transfer gate, a first read transistor connected between the first power node and a second word line, a second read transistor connected between the second power node and the second word line, and an application circuit which is connected to the second word line, and applies a read voltage to the second word line in reading data.

Abstract: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.

Abstract: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

Abstract: A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.

Abstract: A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit line is configured by wirings having the same wiring width and wiring intervals as bit lines configuring the memory cell array and is operated to generate a read timing signal. The second replica bit line is configured by wirings having the same wiring width and wiring intervals as the bit lines configuring the memory cell array and is operated to generate a write timing signal.

Abstract: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

Abstract: A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit which is supplied to an ECC (error connection code) circuit together with remainder bits of the data bits to obtain an error-corrected data which is then supplied to a BIST (Built-In-Self-Test) circuit for testing the error-corrected data obtained from the ECC circuit.

Abstract: Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.

Abstract: A semiconductor device having hierarchized bit lines including an upper-layer bit line and a lower-layer bit line, includes at least one memory cell array to which the lower-layer bit line is connected and a selection transfer gate having an NMOS switching transistor and a PMOS switching transistor to connect the lower-layer bit line to the upper-layer bit line. The NMOS switching transistor and the PMOS switching transistor of the selection transfer gate are arranged opposite to each other in a column direction to sandwich the memory cell array.