Patents by Inventor Osamu Matsuura
Osamu Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10074665Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: GrantFiled: September 6, 2016Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Genki Kawaguchi, Masanori Fujita, Hideki Inokuma, Osamu Matsuura, Takeshi Imamura, Hideo Wada, Makoto Watanabe, Hajime Kaneko, Kenichi Fujii, Takanobu Itoh
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Patent number: 9852942Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a plurality of columnar parts. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode films stacked separately from each other. The plurality of columnar parts is provided in the stacked body. Each of the plurality of columnar parts includes a semiconductor pillar extending in a stacking direction of the stacked body, and a charge storage film provided between the semiconductor pillar and the stacked body. The plurality of electrode films includes a first electrode film provided in upper layers of the stacked body and a second electrode film provided in lower layers of the stacked body. A thickness of the first electrode film is thicker than a thickness of the second electrode film. The first electrode film is provided with a void.Type: GrantFiled: July 5, 2016Date of Patent: December 26, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Wataru Sakamoto, Hideki Inokuma, Osamu Matsuura
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Publication number: 20170263634Abstract: A semiconductor memory device according to the embodiment includes a substrate, electrodes, at least one pillar structure, at least one charge storage film, and at least one insulating member. The electrodes are provided on the substrate, are separately stacked each other, and constitute a stacked body. The electrodes have a first width in a first direction along a surface of the substrate and include a portion extending in a second direction crossing the first direction along the surface. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrodes. The insulating member has a width in the first direction smaller than the first width, pierces the electrodes, and is provided to extend in the stacking direction.Type: ApplicationFiled: September 13, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: HIDEKI INOKUMA, OSAMU MATSUURA, MASANARI FUJITA
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Publication number: 20170229577Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar structure, at least one charge storage film, and a first electrode. The stacked body includes electrode films stacked separately from each other. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrode films. The first electrode is provided in the stacked body, spreads in the stacking direction and a first direction along a surface of the substrate, and contacting the substrate. The first electrode includes a first portion containing a material having conductivity and a second portion containing a material that a linear expansion coefficient is lower than a linear expansion coefficient of silicon, and positioned at a substrate side than the first portion in the stacking direction.Type: ApplicationFiled: September 12, 2016Publication date: August 10, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Osamu MATSUURA, Hideki INOKUMA, Masanari FUJITA
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Publication number: 20170194254Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a plurality of columnar parts. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode films stacked separately from each other. The plurality of columnar parts is provided in the stacked body. Each of the plurality of columnar parts includes a semiconductor pillar extending in a stacking direction of the stacked body, and a charge storage film provided between the semiconductor pillar and the stacked body. The plurality of electrode films includes a first electrode film provided in upper layers of the stacked body and a second electrode film provided in lower layers of the stacked body. A thickness of the first electrode film is thicker than a thickness of the second electrode film. The first electrode film is provided with a void.Type: ApplicationFiled: July 5, 2016Publication date: July 6, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Wataru SAKAMOTO, Hideki INOKUMA, Osamu MATSUURA
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Patent number: 9673214Abstract: A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another.Type: GrantFiled: March 16, 2016Date of Patent: June 6, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masaaki Hatano, Osamu Matsuura
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Publication number: 20170103995Abstract: A semiconductor device according to embodiments described below includes an element region and a peripheral region. The element region is disposed on a substrate and semiconductor elements are collocated in the element region. The peripheral region is disposed on the substrate and surrounds the element region. The element region extends in a first direction parallel to the substrate and includes a plurality of wiring layers laminated on the substrate. The peripheral region includes a peripheral layer arranged to surround the element region. The peripheral layer includes a first part extending in the first direction and a second part extending in a second direction intersecting the first direction. The cross-section structures of the first part and the second part are different from one another.Type: ApplicationFiled: March 16, 2016Publication date: April 13, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HATANO, Osamu MATSUURA
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Publication number: 20170077108Abstract: According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N?2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.Type: ApplicationFiled: September 6, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Genki KAWAGUCHI, Masanari FUJITA, Hideki INOKUMA, Osamu MATSUURA, Takeshi IMAMURA, Hideo WADA, Makoto WATANABE, Hajime KANEKO, Kenichi FUJII, Takanobu ITOH
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Patent number: 9390781Abstract: A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. One of the lower electrode and the upper electrode is connected to an impurity region of the transistor. The second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode. The lower electrode is formed from the same material as the first electrode, the ferroelectric is formed from the same material as the first dielectric, and the upper electrode is formed from the same material as the second electrode.Type: GrantFiled: August 21, 2014Date of Patent: July 12, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Osamu Matsuura
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Publication number: 20150060969Abstract: A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. One of the lower electrode and the upper electrode is connected to an impurity region of the transistor. The second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode. The lower electrode is formed from the same material as the first electrode, the ferroelectric is formed from the same material as the first dielectric, and the upper electrode is formed from the same material as the second electrode.Type: ApplicationFiled: August 21, 2014Publication date: March 5, 2015Inventor: Osamu Matsuura
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Patent number: 8021896Abstract: A semiconductor substrate with an insulating film, a barrier layer containing a metal and formed over the insulating film in a region that includes a peripheral edge part of a semiconductor substrate, a capacitor lower electrode layer formed on the barrier layer and having an edge-cut on the peripheral edge part of the semiconductor substrate, an oxide layer formed on the barrier layer at the peripheral edge part where the barrier layer is not covered by the lower electrode layer, a ferroelectric layer formed on the lower electrode layer and the oxide layer, and a capacitor upper electrode layer formed over the ferroelectric layer.Type: GrantFiled: February 13, 2008Date of Patent: September 20, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Osamu Matsuura
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Publication number: 20110183440Abstract: A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes the steps of forming a contact plug in an insulation film so as to be connected to an element on a semiconductor substrate, applying PLA pretreatment to the insulation film in an NH3 atmosphere, forming a Ti film over the contact plug, nitriding the Ti film to form a TiN film as a part of a lower electrode of a capacitor, and forming a metal film as another part of the lower electrode of the capacitor on the titanium nitride film.Type: ApplicationFiled: April 7, 2011Publication date: July 28, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Osamu Matsuura
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Publication number: 20110120130Abstract: A fossil fuel combustion thermal power system including a carbon dioxide separation and capture unit comprising a fossil fuel combustion thermal power system including a boiler for burning fossil fuel and generating steam and a steam turbine including a high-pressure turbine driven by the steam generated by the boiler for generating power, and a carbon dioxide separation and capture unit.Type: ApplicationFiled: November 23, 2010Publication date: May 26, 2011Applicant: Hitachi, Ltd.Inventors: Nobuyoshi MISHIMA, Takashi SUGIURA, Osamu MATSUURA, Tetsuya KOSAKA
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Patent number: 7698717Abstract: A system for recording/reproducing a photosensitive recording medium, comprising: a photosensitive recording medium cartridge including a cartridge body, a shutter, and a lock mechanism as defined herein; and a recording/reproducing device including a housing, an insertion port shutter, an unlock mechanism, and a shutter opening mechanism as defined herein.Type: GrantFiled: August 17, 2006Date of Patent: April 13, 2010Assignee: FUJIFILM CorporationInventors: Katsuyoshi Asakura, Tomoyuki Takahashi, Osamu Matsuura
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Patent number: 7657660Abstract: The present invention provides an input/output device capable of bringing a per-unit input/output circuit into a simple configuration without impairing reliability even when logic levels opposite in polarity are outputted between input/output devices made conductive to the outside. The input/output device is equipped with one reference port Pk selected from a port group which inputs and outputs signals, target ports Pt selected from other than the reference port of the port group, and a conduction detector which detects that conduction is made between input/output terminals for the reference port Pk and the target ports Pt.Type: GrantFiled: February 2, 2007Date of Patent: February 2, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Kazuya Taniguchi, Osamu Matsuura, Kazuo Ohno
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Patent number: 7633107Abstract: On forming a ferroelectric capacitor structure, an IrO2 film and an IrOx film which are constituents of an upper electrode layer are sequentially formed on a capacitor film. By RTA treatment at 600° C. to 750° C., in this case, at 725° C. for about one minute under an O2 atmosphere, only a surface layer of the IrOx film is oxidized, and a highly oxidized layer which is higher in oxidation degree as compared with the other portion of the IrOx film is formed.Type: GrantFiled: August 17, 2006Date of Patent: December 15, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Osamu Matsuura
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Patent number: 7624407Abstract: A photosensitive recording medium cartridge comprising: a photosensitive recording medium; a cartridge body including a disc storage portion where the photosensitive recording medium is received rotatably, an opening portion formed in a side surface of the cartridge body in an insertion direction, shutter slide surfaces offset inward and formed in an outer surface of the cartridge body so as to be connected to the opening portion-side side surface, and an inner opening for exposing a center and a recording surface of the photosensitive recording medium to the outside; a shutter as defined herein; and a lid fixed to the side surface of the cartridge body so as to close the opening portion, wherein the shutter is attached to the shutter slide surfaces while the movement of the shutter is limited by the lid and first step portions formed in boundaries between the shutter slide surfaces and the outer surface.Type: GrantFiled: August 23, 2006Date of Patent: November 24, 2009Assignee: FUJIFILM CorporationInventors: Katsuyoshi Asakura, Osamu Matsuura, Tomoyuki Takahashi
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Patent number: 7528561Abstract: A linear drive apparatus comprising: a guide having an internal body; a slider moved along the guide, a driving mechanism for generating a driving force by magnetic interaction of the slider with the guide so as to linearly drive the slider; and a magnetic measurement unit having a magnetic scale and a detector which are opposed to each other and change a relative position relative to each other in order to obtain the relative position of the slider relative to the guide, wherein an opposing direction of the magnetic scale and the detector is the direction of the outer circumference of the guide, and the detector detects a signal from the magnetic scale in accordance with the relative position of the slider, whereby the relative position of the slider is obtained.Type: GrantFiled: February 7, 2007Date of Patent: May 5, 2009Assignee: Fanuc LtdInventors: Tomohiko Kawai, Kenzo Ebihara, Osamu Matsuura
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Patent number: 7521745Abstract: A bottom electrode (52) made of Ir, an initial layer (53), a core layer (54) and a termination layer (55) of a PZT film, and a top electrode (56) made of IrO2, are formed on an underlining film (51). The initial layer (53) is formed in a low oxygen partial pressure with a thickness of 5 nm. The thickness of the core layer (54) is set to 120 nm. The termination layer (55) is set to be an excess Zr layer. In other words, as for the composition of the termination layer (55), “Zr/(Zr+Ti)” is set to be larger than 0.5, and in the termination layer (55) Zr is contained more excessively than the morphotropic phase boundary composition.Type: GrantFiled: October 13, 2006Date of Patent: April 21, 2009Assignee: Fujitsu LimitedInventors: Shigeyoshi Umemiya, Osamu Matsuura
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Publication number: 20080191254Abstract: A semiconductor substrate with an insulating film, a barrier layer containing a metal and formed over the insulating film in a region that includes a peripheral edge part of a semiconductor substrate, a capacitor lower electrode layer formed on the barrier layer and having an edge-cut on the peripheral edge part of the semiconductor substrate, an oxide layer formed on the barrier layer at the peripheral edge part where the barrier layer is not covered by the lower electrode layer, a ferroelectric layer formed on the lower electrode layer and the oxide layer, and a capacitor upper electrode layer formed over the ferroelectric layer.Type: ApplicationFiled: February 13, 2008Publication date: August 14, 2008Applicant: FUJITSU LIMITEDInventor: Osamu Matsuura