Patents by Inventor Osamu Miyata
Osamu Miyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8164201Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.Type: GrantFiled: June 28, 2006Date of Patent: April 24, 2012Assignee: Rohm Co., Ltd.Inventors: Masaki Kasai, Osamu Miyata
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Publication number: 20120032325Abstract: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.Type: ApplicationFiled: October 17, 2011Publication date: February 9, 2012Applicant: ROHM CO., LTD.Inventors: Osamu MIYATA, Shingo Higuchi
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Patent number: 8063495Abstract: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.Type: GrantFiled: October 3, 2006Date of Patent: November 22, 2011Assignee: Rohm Co., Ltd.Inventors: Osamu Miyata, Shingo Higuchi
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Patent number: 7928581Abstract: A manufacture method for semiconductor device (1, 21) including: a sealing-resin-layer forming step of forming a sealing resin layer (7) on a conductive member (13) formed at lest on one surface of a base substrate (11) formed with a plurality of wiring boards (2) therein, the conductive member spanning a boundary between a respective pair of adjoining wiring boards; and a step of moving the base substrate and a cutting tool (B) relative to each other in a manner to allow the cutting tool to pass through the base substrate from the other surface (2b) opposite from the one surface thereof toward the one surface thereof, thereby cutting the base substrate along the boundary between the respective pair of adjoining wiring boards.Type: GrantFiled: October 17, 2005Date of Patent: April 19, 2011Assignee: Rohm Co., Ltd.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20100187659Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.Type: ApplicationFiled: March 26, 2010Publication date: July 29, 2010Applicant: ROHM CO., LTD.Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
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Patent number: 7714448Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.Type: GrantFiled: November 16, 2005Date of Patent: May 11, 2010Assignee: Rohm Co., Ltd.Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
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Patent number: 7688008Abstract: A lighting lamp 1 using LED lamps as a light source can include a delay circuit 5, a power supply control unit 6, and a timer circuit 7. The delay circuit 5 can be configured to cause the luminous intensity of the LED lamps to rise along a predetermined slope upon turning on the lighting lamp. The power supply control unit and the timer circuit can be configured to cause the luminous intensity of the LED lamps to fall along a predetermined slope which has an inflection point P at a predetermined time point along the slope.Type: GrantFiled: November 22, 2006Date of Patent: March 30, 2010Assignee: Stanley Electric Co., Ltd.Inventors: Daisuke Uchida, Osamu Miyata, Toshiyuki Kondo
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Patent number: 7598613Abstract: A semiconductor device is provided with: a solid device having a connection surface formed with a connection electrode projected therefrom; a semiconductor chip which has a functional surface formed with a metal bump projected therefrom and which is bonded to the connection surface of the solid device as directing its functional surface to the connection surface and maintaining a predetermined distance between the functional surface and the connection surface; and a connecting member containing a low melting point metal having a lower solidus temperature than that of the connection electrode and the bump, and interconnecting the connection electrode and the bump. A sum of a height of the connection electrode and a height of the bump is not less than a half of the predetermined distance.Type: GrantFiled: September 1, 2005Date of Patent: October 6, 2009Assignee: Rohm Co., Ltd.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20090224409Abstract: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.Type: ApplicationFiled: October 3, 2006Publication date: September 10, 2009Applicant: ROHM CO., LTD.Inventors: Osamu Miyata, Shingo Higuchi
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Publication number: 20090127705Abstract: There are provided a semiconductor device capable of accurately determining whether a semiconductor chip is bonded to a solid-state device such as the other semiconductor chip parallelly with each other, a semiconductor chip used for the semiconductor device, and a method of manufacturing the semiconductor chip. The semiconductor chip includes a functional bump projected with a first projection amount from the surface of the semiconductor chip and electrically connecting the semiconductor chip to the solid-state device, and a connection confirmation bump projected with a second projection amount, which is smaller than the first projection amount, from the surface of the semiconductor chip and used for confirming the state of the electrical connection by the functional bump.Type: ApplicationFiled: August 18, 2006Publication date: May 21, 2009Applicant: ROHM CO., LTD.Inventors: Osamu Miyata, Tadahiro Morifuji
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Publication number: 20090121347Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.Type: ApplicationFiled: June 28, 2006Publication date: May 14, 2009Applicant: ROHM CO., LTD.Inventors: Masaki Kasai, Osamu Miyata
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Patent number: 7518230Abstract: A semiconductor chip according to the present invention is a semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of the surface thereof, and having the surface thereof opposed to and joined to the surface of a solid-state device.Type: GrantFiled: December 13, 2006Date of Patent: April 14, 2009Assignee: Rohm Co., LtdInventors: Osamu Miyata, Tadahiro Morifuji
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Patent number: 7456049Abstract: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its mounting surface is exposed from the sealing resin. The method includes a lead forming step for forming the lead, and a side edge coining step for subjecting a side edge of a sealed surface, which is a surface on the opposite side of the mounting surface, of the lead to coining processing from the side of the sealed surface, to form a slipping preventing portion. The slipping preventing portion is to project sideward from the lead and to have a slipping preventing surface between the mounting surface and the sealed surface of the lead.Type: GrantFiled: January 4, 2006Date of Patent: November 25, 2008Assignee: Rohm Co., Ltd.Inventor: Osamu Miyata
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Patent number: 7456502Abstract: The invention provides a wiring board (2,15) to which a semiconductor chip (3) is to be bonded while directing a surface of the semiconductor chip toward the wiring board. The wiring board includes a connection electrode (14) that is formed on a bonding surface (2a, 15a) to which the semiconductor chip is to be bonded and that is used to make a connection with the semiconductor chip, an insulating film (6) that is formed on the bonding surface and that has an opening (6a) to expose the connection electrode, and a low-melting-point metallic part (16) that is provided on the connection electrode in the opening and that is made of a low-melting-point metallic material whose solidus temperature is lower than that of the connection electrode.Type: GrantFiled: August 4, 2005Date of Patent: November 25, 2008Assignee: Rohm Co., Ltd.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20080272488Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a functional surface formed with a functional element, an electrode pad provided directly on the functional element on the functional surface of the semiconductor chip, a protective resin layer laminated on the functional surface of the semiconductor chip, an external connection terminal provided on the protective resin layer in opposed relation to the electrode pad, and a post extending through the protective resin layer in a direction in which the electrode pad and the external connection terminal are opposed to each other for connection between the electrode pad and the external connection terminal.Type: ApplicationFiled: September 26, 2005Publication date: November 6, 2008Applicant: ROHM CO., LTD.Inventors: Osamu Miyata, Takuya Kadoguchi, Masaki Kasai
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Patent number: 7436063Abstract: A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.Type: GrantFiled: October 4, 2005Date of Patent: October 14, 2008Assignee: Rohm Co., Ltd.Inventors: Osamu Miyata, Shingo Higuchi
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Publication number: 20080246163Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.Type: ApplicationFiled: July 21, 2005Publication date: October 9, 2008Inventors: Kazumasa Tanida, Osamu Miyata
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Patent number: 7405485Abstract: A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.Type: GrantFiled: June 9, 2005Date of Patent: July 29, 2008Assignee: Rohm Co., Ltd.Inventors: Kazumasa Tanida, Tadahiro Morifuji, Osamu Miyata
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Publication number: 20080036043Abstract: A manufacture method for semiconductor device (1, 21) including: a sealing-resin-layer forming step of forming a sealing resin layer (7) on a conductive member (13) formed at lest on one surface of a base substrate (11) formed with a plurality of wiring boards (2) therein, the conductive member spanning a boundary between a respective pair of adjoining wiring boards; and a step of moving the base substrate and a cutting tool (B) relative to each other in a manner to allow the cutting tool to pass through the base substrate from the other surface (2b) opposite from the one surface thereof toward the one surface thereof, thereby cutting the base substrate along the boundary between the respective pair of adjoining wiring boards.Type: ApplicationFiled: October 17, 2005Publication date: February 14, 2008Applicant: ROHM CO., LTD.Inventors: Kazumasa Tanida, Osamu Miyata
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Publication number: 20080006910Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.Type: ApplicationFiled: November 16, 2005Publication date: January 10, 2008Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi