Abstract: This invention relates to a composition, kit, or DNA chip comprising polynucleotides and antibodies as probes for detecting, determining, or predicting the presence or metastasis of esophageal cancer, and to a method for detecting, determining, or predicting the presence or metastasis of esophageal cancer using the same.

Abstract: An information processing apparatus, includes: a plurality of processor means respectively including storage means for storing analog information and comparison means for comparing analog information stored in the storage means with an inputted reference analog value; input means for inputting the reference analog value to the plurality of processor means while changing the reference analog value in synchronization with a clock signal; and counter means for updating a count value in synchronization with the clock signal and outputting the count value when the analog information and the reference analog value become consistent at a corresponding comparison means.

Abstract: This invention relates to a composition, kit, or DNA chip comprising polynucleotides and antibodies as probes for detecting, determining, or predicting the presence or metastasis of esophageal cancer, and to a method for detecting, determining, or predicting the presence or metastasis of esophageal cancer using the same.

Abstract: An object of the invention is to provide a casting nozzle in which attachment and deposition of alumina or the like can be prevented while a drift of molten steel can be prevented. The casting nozzle according to the invention is characterized in that the casting nozzle has a molten steel flow hole portion in which “a plurality of independent protrusion portions and/or concave portions” are disposed so that each of the protrusion portions and/or concave portions has a size satisfying the expression (1): H?2 mm and the expression (2): L>2×H mm [in which “H” shows the maximum height of the protrusion portion or the maximum depth of the concave portion, and “L” shows the maximum length of a base portion of the protrusion portion or concave portion].

Abstract: An information processing apparatus includes a preliminary learning unit configured to learn a preliminary discriminator for a respective one of a plurality of combinations of variations in variation categories in a discrimination target pattern, a branch structure determination unit configured to perform discrimination processing using the preliminary discriminator and to determine a branch structure of a main discriminator based on a result of the discrimination processing, and a main learning unit configured to learn the main discriminator based on the branch structure.

Abstract: Learning is sequentially executed with respect to weak discriminators based on learning data held in a storage device. Upon learning, an evaluation value for the weak discriminator is calculated. It is discriminated, based on a shift of the evaluation value, whether or not the learning is overlearning. If it is discriminated that the learning is overlearning, new learning data is added. Thus, the overlearning is easily detected and the learning is efficiently executed.

Abstract: A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.

Abstract: This invention relates to a composition, kit, DNA chip, and use thereof for detecting, diagnosing, and predicting metastasis of kidney cancer and/or for predicting the prognosis for kidney cancer, comprising one or a plurality of polynucleotides selected from the group consisting of polynucleotides, mutants thereof or fragments thereof, the expression levels of which vary in kidney cancer cells from a patient with a poor prognosis when compared with that in kidney cancer cells from a patient with a good prognosis; or antibodies or fragments thereof that bind specifically to polypeptides, mutants thereof or fragments thereof, the expression levels of which vary in the similar manner.

Abstract: This invention is directed to an analysis chip comprising a substrate having a surface on which a selective binding substance is immobilized; a cover member adhered to the substrate; and particles movably contained or injected in a void between the substrate and the cover member; wherein the surfaces of the particles are coated with a surfactant. By this invention, generation of bubbles which inhibit the selective reaction between the test substance and the immobilized selective binding substance is suppressed, thereby reducing the deviation of data, suppressing the lowering of sensitivity, and promoting the reproducibility of the measurement.

Abstract: This invention relates to a composition, kit, or DNA chip comprising polynucleotides and antibodies as probes for detecting, determining, or predicting the presence or metastasis of esophageal cancer, and to a method for detecting, determining, or predicting the presence or metastasis of esophageal cancer using the same.

Abstract: An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.

Abstract: A pattern identification unit generation method of generating a pattern identification unit in which a weak discriminator array obtained by cascade-connecting a plurality of weak discriminators branches, and weak discriminator arrays are connected to respective arms after branching, evaluates based on a processing result obtained by inputting a set of evaluation data to the weak discriminator array whether or not a weak discriminator array after branching reaches the number of stages to be connected. The number of stages of weak discriminators to be connected without branching as the weak discriminator array is determined based on this evaluation result.

Abstract: A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0–11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n?1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.

Abstract: A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.

Abstract: An object of the invention is to provide a casting nozzle in which attachment and deposition of alumina or the like can be prevented while a drift of molten steel can be prevented. The casting nozzle according to the invention is characterized in that the casting nozzle has a molten steel flow hole portion in which “a plurality of independent protrusion portions and/or concave portions” are disposed so that each of the protrusion portions and/or concave portions has a size satisfying the expression (1): H?2 mm and the expression (2): L>2×H mm [in which “H” shows the maximum height of the protrusion portion or the maximum depth of the concave portion, and “L” shows the maximum length of a base portion of the protrusion portion or concave portion].

Abstract: A pattern recognition apparatus for detecting a predetermined pattern contained in an input signal is provided with plural detecting processing parts and for detecting respectively different features for a same input, plural integrating processing parts for spatially integrating, for each process results, the features detected by the plural detecting processing parts, plural detecting memories for retaining the process results of the detecting processing parts, plural integrating memories for retaining the process results of the integrating processing parts, a global data line 1030 to which all the predetermined detecting processing parts and all the predetermined integrating memories are connected at a certain timing, and plural local data lines each of which is connected to a predetermined set of the detecting processing parts, the integrating processing parts and the detecting memory.