Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.

Abstract: An image processing system includes a generating unit and a storing unit. The generating unit determines a subject included in a wide-angle image and generate a partial image including the subject from the wide-angle image. The storing unit stores the partial image in association with the wide-angle image from which the partial image is extracted.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

Abstract: A learning device includes an encoding unit, a plurality of permutation units, a plurality of decoding units, a selection unit, and a learning unit. The encoding unit is configured generate an encoded word by encoding a transmission word. The permutation units are configured to permutate the encoded word according to different permutation manners to generate a plurality of permutated encoded words. The decoding units are configured to perform message passing decoding on the plurality of permutated encoded words, to generate a plurality of decoded words. The message passing decoding involves weighting of values of a word transmitted during the message passing decoding. The selection unit is configured to select one or more of the decoded words. The learning unit is configured to perform learning of weighting values of the weighting based on the transmission word and the selected one or more of the decoded words.

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.

Abstract: An information processing method is performed by an information processing apparatus including a communication interface and an imaging device. The method includes acquiring a wide-angle image from an external imaging device via the communication interface; invoking an imaging function implemented by the imaging device; acquiring a captured image imaged by the imaging device; and associating the acquired wide-angle image with the acquired captured image.

Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: A memory controller according to an embodiment includes a first decoder which calculates first extrinsic value based on a decoding success rate specified using a first table showing a correspondence between first distance information indicating a square Euclidean distance between a first decode word and a first soft input value and a first decoding success rate indicating a probability of a decoding result that the first decode word is correct, and a second decoder which calculates second extrinsic value based on a decoding success rate specified using the second table showing a correspondence second distance information indicating a square Euclidean distance between a second decode word and a second soft input value and a second decoding success rate indicating a probability of a decoding result that the second decode word is correct.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimens