Patents by Inventor Osamu Torii
Osamu Torii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103470Abstract: An information processing apparatus that updates a regression coefficient parameter based on a predetermined objective function including a regularization term for each of a plurality of elements characterized by a task and a feature value, the information processing apparatus comprising processing circuitry. The processing circuitry selects an element which is an update target of the regression coefficient parameter from the plurality of elements, fixes a value of the regularization term of an unselected element, selects a calculation expression for updating a regression coefficient parameter of the selected element based on a regression coefficient parameter of the unselected element, and updates the regression coefficient parameter of the selected element based on the selected calculation expression.Type: ApplicationFiled: August 25, 2023Publication date: March 28, 2024Applicant: Kioxia CorporationInventors: Yuma YOSHINAGA, Atsushi MAESONO, Osamu TORII, Shinichiro TOMIOKA, Shinichiro MANABE
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Publication number: 20240095306Abstract: An information processing apparatus comprising processing circuitry. The processing circuitry is configured to acquire objective variables and explanatory variables which are regression analysis targets, extract a plurality of first explanatory variables having a high degree of influence on the objective variable from among the explanatory variables by sparse modeling using a first regression equation, and extract a second explanatory variable having a high degree of influence on the plurality of first explanatory variables by sparse modeling using a second regression equation.Type: ApplicationFiled: August 21, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventors: Osamu TORII, Shinichiro MANABE
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Publication number: 20230328383Abstract: An information processing method is performed by an information processing apparatus including a communication interface and an imaging device. The method includes acquiring a wide-angle image from an external imaging device via the communication interface; invoking an imaging function implemented by the imaging device; acquiring a captured image imaged by the imaging device; and associating the acquired wide-angle image with the acquired captured image.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Applicant: Ricoh Company, Ltd.Inventors: Yusuke FUKUOKA, Osamu TORII, Kohei MARUMOTO
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Publication number: 20230306582Abstract: An information processing apparatus has an objective variable acquirer configured to acquire a multi-dimensional objective variable, an objective variable dimension compressor configured to compress the number of dimensions of the objective variable, an explanatory variable acquirer configured to acquire an explanatory variable, and an influence degree calculator configured to set at least one of a basis characterizing the objective variable and a coefficient weighting the basis as a new objective variable and calculate an influence degree on the new objective variable by using the explanatory variable.Type: ApplicationFiled: September 12, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Masahiro HAYASHI, Shinichiro MANABE, Osamu TORII, Tatsuya ZETTSU, Hiroshi FUJITA, Ryota YOSHIZAWA
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Publication number: 20230290407Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: ApplicationFiled: May 22, 2023Publication date: September 14, 2023Applicant: KIOXIA CORPORATIONInventors: Tomonori TAKAHASHI, Masanobu SHIRAKAWA, Osamu TORII, Marie TAKADA
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Publication number: 20230275601Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Applicant: KIOXIA CORPORATIONInventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
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Patent number: 11699486Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: GrantFiled: May 6, 2022Date of Patent: July 11, 2023Assignee: KIOXIA CORPORATIONInventors: Tomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
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Patent number: 11683053Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: GrantFiled: February 18, 2021Date of Patent: June 20, 2023Assignee: KIOXIA CORPORATIONInventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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Patent number: 11567830Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.Type: GrantFiled: February 24, 2021Date of Patent: January 31, 2023Assignee: KIOXIA CORPORATIONInventors: Yuma Yoshinaga, Tomoya Kodama, Osamu Torii, Kenichiro Furuta, Ryota Yoshizawa
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Publication number: 20220321796Abstract: An image processing system includes a generating unit and a storing unit. The generating unit determines a subject included in a wide-angle image and generate a partial image including the subject from the wide-angle image. The storing unit stores the partial image in association with the wide-angle image from which the partial image is extracted.Type: ApplicationFiled: September 4, 2020Publication date: October 6, 2022Applicant: Ricoh Company, Ltd.Inventors: Osamu TORII, Kohei MARUMOTO, Yusuke FUKUOKA
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Publication number: 20220270678Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: ApplicationFiled: May 6, 2022Publication date: August 25, 2022Applicant: KIOXIA CORPORATIONInventors: Tomonori TAKAHASHI, Masanobu SHIRAKAWA, Osamu TORII, Marie TAKADA
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Patent number: 11418219Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.Type: GrantFiled: August 27, 2020Date of Patent: August 16, 2022Assignee: KIOXIA CORPORATIONInventors: Ryota Yoshizawa, Kenichiro Furuta, Yuma Yoshinaga, Osamu Torii, Tomoya Kodama
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Patent number: 11361820Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: GrantFiled: January 7, 2021Date of Patent: June 14, 2022Assignee: KIOXIA CORPORATIONInventors: Tomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
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Patent number: 11347584Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.Type: GrantFiled: March 3, 2020Date of Patent: May 31, 2022Assignee: Kioxia CorporationInventors: Masanobu Shirakawa, Hideki Yamada, Marie Takada, Ryo Yamaki, Osamu Torii, Naomi Takeda
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Publication number: 20210295153Abstract: A learning device includes an encoding unit, a plurality of permutation units, a plurality of decoding units, a selection unit, and a learning unit. The encoding unit is configured generate an encoded word by encoding a transmission word. The permutation units are configured to permutate the encoded word according to different permutation manners to generate a plurality of permutated encoded words. The decoding units are configured to perform message passing decoding on the plurality of permutated encoded words, to generate a plurality of decoded words. The message passing decoding involves weighting of values of a word transmitted during the message passing decoding. The selection unit is configured to select one or more of the decoded words. The learning unit is configured to perform learning of weighting values of the weighting based on the transmission word and the selected one or more of the decoded words.Type: ApplicationFiled: February 24, 2021Publication date: September 23, 2021Inventors: Ryota YOSHIZAWA, Kenichiro FURUTA, Yuma YOSHINAGA, Osamu TORII, Tomoya KODAMA
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Publication number: 20210279133Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.Type: ApplicationFiled: February 24, 2021Publication date: September 9, 2021Applicant: Kioxia CorporationInventors: Yuma YOSHINAGA, Tomoya KODAMA, Osamu TORII, Kenichiro FURUTA, Ryota YOSHIZAWA
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Publication number: 20210250500Abstract: An information processing method is performed by an information processing apparatus including a communication interface and an imaging device. The method includes acquiring a wide-angle image from an external imaging device via the communication interface; invoking an imaging function implemented by the imaging device; acquiring a captured image imaged by the imaging device; and associating the acquired wide-angle image with the acquired captured image.Type: ApplicationFiled: January 12, 2021Publication date: August 12, 2021Inventors: Yusuke FUKUOKA, Osamu TORII, Kohei MARUMOTO
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Publication number: 20210242888Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.Type: ApplicationFiled: August 27, 2020Publication date: August 5, 2021Inventors: Ryota YOSHIZAWA, Kenichiro FURUTA, Yuma YOSHINAGA, Osamu TORII, Tomoya KODAMA
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Publication number: 20210175907Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Applicant: Toshiba Memory CorporationInventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
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Publication number: 20210134360Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.Type: ApplicationFiled: January 7, 2021Publication date: May 6, 2021Applicant: Toshiba Memory CorporationInventors: Tomonori TAKAHASHI, Masanobu SHIRAKAWA, Osamu TORII, Marie TAKADA