Patents by Inventor Osamu Torii

Osamu Torii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10467090
    Abstract: A memory controller according to an embodiment includes a first decoder which calculates first extrinsic value based on a decoding success rate specified using a first table showing a correspondence between first distance information indicating a square Euclidean distance between a first decode word and a first soft input value and a first decoding success rate indicating a probability of a decoding result that the first decode word is correct, and a second decoder which calculates second extrinsic value based on a decoding success rate specified using the second table showing a correspondence second distance information indicating a square Euclidean distance between a second decode word and a second soft input value and a second decoding success rate indicating a probability of a decoding result that the second decode word is correct.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Osamu Torii, Haruka Obata
  • Patent number: 10432231
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Publication number: 20190273516
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 5, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Riki SUZUKI, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Patent number: 10230401
    Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimens
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga, Osamu Torii
  • Patent number: 10089241
    Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
  • Patent number: 10014980
    Abstract: According to one embodiment, a communication device 1 operating as a publisher calculates parity of a certain size which is capable of being commonly used for each of different data units from data to be sent each time receiving a lost notification from one or more communication device 1 operating as subscribers, the lost notification indicating that one or more data units are lost, and sends the calculated parity to the one or more communication devices 1 operating as the subscribers.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kenichi Maeda, Yujen Lai, Yosuke Bando, Hironori Uchikawa, Osamu Torii
  • Patent number: 9927990
    Abstract: According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Osamu Torii, Tokumasa Hara, Hironori Uchikawa
  • Patent number: 9891848
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii
  • Patent number: 9876511
    Abstract: A memory system includes a non-volatile memory. A coding unit generates a codeword by performing coding of a graph code using a graph. A side of the graph is associated with a block that is a part of user data and that has one or more symbols at which component codes intersect one another. A control unit stores the codeword in the non-volatile memory. Error correction is performed on the user data in accordance with the codeword.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Osamu Torii, Yoshiyuki Sakamaki
  • Publication number: 20170262379
    Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa HARA, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
  • Publication number: 20170263331
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non-volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold-voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 14, 2017
    Inventors: Juan Shi, Hironori Uchikawa, Tokumasa Hara, Osamu Torii
  • Patent number: 9761325
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the non -volatile memory, a code processor that generates a code word by encoding; and a controller that sets a threshold -voltage read level for determining whether a value of each bit in a received word read out from the non-volatile memory is “0” or “1”. A difference between the number of bits which have value equals “0” and the number of bits which have value equals “1” in the code word depends on a code rate of the encoding. The controller obtains the threshold-voltage read level based on the code rate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Juan Shi, Hironori Uchikawa, Tokumasa Hara, Osamu Torii
  • Publication number: 20170257298
    Abstract: According to one embodiment, a communication device 1 operating as a publisher calculates parity of a certain size which is capable of being commonly used for each of different data units from data to be sent each time receiving a lost notification from one or more communication device 1 operating as subscribers, the lost notification indicating that one or more data units are lost, and sends the calculated parity to the one or more communication devices 1 operating as the subscribers.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 7, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Yujen Lai, Yosuke Bando, Hironori Uchikawa, Osamu Torii
  • Publication number: 20170257122
    Abstract: A memory controller according to an embodiment includes a first decoder which calculates first extrinsic value based on a decoding success rate specified using a first table showing a correspondence between first distance information indicating a square Euclidean distance between a first decode word and a first soft input value and a first decoding success rate indicating a probability of a decoding result that the first decode word is correct, and a second decoder which calculates second extrinsic value based on a decoding success rate specified using the second table showing a correspondence second distance information indicating a square Euclidean distance between a second decode word and a second soft input value and a second decoding success rate indicating a probability of a decoding result that the second decode word is correct.
    Type: Application
    Filed: September 8, 2016
    Publication date: September 7, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Osamu TORII, Haruka OBATA
  • Publication number: 20170187395
    Abstract: According to an embodiment, a memory controller for controlling a nonvolatile memory in which multi-dimensional error correction code having two or more component codes is stored, the memory controller configured to read out the multi-dimensional error correction code; acquire a received word of the multi-dimensional error correction code; hold an intermediate decoded word of the multi-dimensional error correction code; perform a first decoding process which is decoding a first component code included in the intermediate decoded word; when a first error symbol included in the first component code is detected by the first decoding process, perform a first rewriting process which is rewriting a value corresponding to the first error symbol in the intermediate decoded word, and record first recurrence information for reproducing a value of the first error symbol before rewriting; perform a second decoding process which is decoding a second component code included in the intermediate decoded word, of which dimens
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daiki Watanabe, Daisuke Fujiwara, Kosuke Morinaga, Osamu Torii
  • Patent number: 9648382
    Abstract: A display apparatus connected to a content server via a network, includes a content acquisition unit that acquires content with an input format; an input format detection unit that detects an input format of content to be acquired; a storage unit that stores information on the content server connected to the display apparatus; a server search unit that searches for a content server in the network; and a server connection unit that, upon the input format detection unit detecting that the input format of the content to be acquired is an input format of content acquired from a content server, connects to at least one of a content server specified by the information stored in the storage unit and a content server searched for and detected by the server search unit.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 9, 2017
    Assignee: Ricoh Company, Ltd.
    Inventors: Rie Nakamura, Daisuke Sakai, Osamu Torii, Hiroki Ozaki, Kazuya Fujikawa
  • Patent number: 9606613
    Abstract: An image display apparatus capable of performing communications via a network includes an energy-saving state shifting part to shift an energy state to an energy-saving state in which energy consumption is suppressed, a shifting time setting part to set a time required for shifting to the energy-saving state in accordance with a state or an environment of the image display apparatus, a data input detector to detect presence or absence of data input into the image display apparatus, and an operations detector to detect whether an operation on the image display apparatus is being performed by a user. When neither data input nor operation performed on the image display apparatus is detected by the operations detector, and when the time required for shifting to the energy-saving state set by the shifting time setting part has elapsed, the energy-saving state shifting part shifts the energy state to the energy-saving state.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 28, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventors: Osamu Torii, Daisuke Sakai
  • Patent number: 9600364
    Abstract: According to an embodiment, a row decoder to perform row decoding by using, as row soft input information, a row received word read as soft determination information from a non-volatile memory and to calculate row extrinsic information and a column decoder to perform column decoding by using column soft input information, which is a result of adding of the row extrinsic information to a column received word read as soft determination information from the non-volatile memory, and to calculate column extrinsic information are included. The row decoder includes a first decoder for first decoding, a second decoder for second decoding a decoding method of which is different from that of the first decoding, and a selection unit to select a decoded result based on accuracy of a decoded result of the first decoding and that of a decoded result of the second decoding and to calculate the row extrinsic information.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Torii, Haruka Obata, Ryo Yamaki, Daiki Watanabe
  • Publication number: 20170075599
    Abstract: According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.
    Type: Application
    Filed: March 10, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Osamu TORII, Tokumasa HARA, Hironori UCHIKAWA
  • Publication number: 20170077958
    Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a coding unit that generates a codeword by performing coding of a graph code using a graph of which a side is associated with a block, the block being a part of user data and having one or more symbols at which component codes intersect one another; and a control unit that stores the codeword in the non-volatile memory.
    Type: Application
    Filed: March 8, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Osamu TORII, Yoshiyuki SAKAMAKI