Abstract: A trading management server (listing information registration device) accepts input of an item code associated with an item to be listed, acquires default information to be associated with the accepted item code, displays and outputs a listing information form in which the acquired default information is input as a default value, registers, in a listing information database, a piece of listing information edited in the listing information form, when input of the item code is accepted, retrieves at least one another piece of listing information including the accepted item code from pieces of listing information registered in the listing information database, and displays and outputs, together with the listing information form, summary information of the retrieved at least one another piece of listing information.

Abstract: An information processing apparatus includes a first neural network that extracts a feature of a query image and features of search object images; a processing circuitry detects a degree of similarity between the search object images and a query image based on the feature of the query image and the features of the search object images, and calculates a score of each of the search object images based on the degree of similarity between each of the search object images and the query image and feature transformation information relating to the degree of similarity between each of the search object images and the query image; a second neural network that outputs the feature transformation information; and a user interface that determines by a user the feature transformation information of each of the search object images based on the degree of similarity or the scores of the search object images.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: An image processing system includes a generating unit and a storing unit. The generating unit determines a subject included in a wide-angle image and generate a partial image including the subject from the wide-angle image. The storing unit stores the partial image in association with the wide-angle image from which the partial image is extracted.

Abstract: An information processing apparatus that updates a regression coefficient parameter based on a predetermined objective function including a regularization term for each of a plurality of elements characterized by a task and a feature value, the information processing apparatus comprising processing circuitry. The processing circuitry selects an element which is an update target of the regression coefficient parameter from the plurality of elements, fixes a value of the regularization term of an unselected element, selects a calculation expression for updating a regression coefficient parameter of the selected element based on a regression coefficient parameter of the unselected element, and updates the regression coefficient parameter of the selected element based on the selected calculation expression.

Abstract: An information processing apparatus comprising processing circuitry. The processing circuitry is configured to acquire objective variables and explanatory variables which are regression analysis targets, extract a plurality of first explanatory variables having a high degree of influence on the objective variable from among the explanatory variables by sparse modeling using a first regression equation, and extract a second explanatory variable having a high degree of influence on the plurality of first explanatory variables by sparse modeling using a second regression equation.

Abstract: An information processing method is performed by an information processing apparatus including a communication interface and an imaging device. The method includes acquiring a wide-angle image from an external imaging device via the communication interface; invoking an imaging function implemented by the imaging device; acquiring a captured image imaged by the imaging device; and associating the acquired wide-angle image with the acquired captured image.

Abstract: An information processing apparatus has an objective variable acquirer configured to acquire a multi-dimensional objective variable, an objective variable dimension compressor configured to compress the number of dimensions of the objective variable, an explanatory variable acquirer configured to acquire an explanatory variable, and an influence degree calculator configured to set at least one of a basis characterizing the objective variable and a coefficient weighting the basis as a new objective variable and calculate an influence degree on the new objective variable by using the explanatory variable.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read a received word from the non-volatile memory, estimate noise by using a plurality of different models for estimating the noise included in the received word to obtain a plurality of noise estimation values, select one noise estimation value from the plurality of noise estimation values, update the received word by using a value obtained by subtracting the selected noise estimation value from the read received word, and decode the updated received word by using a belief-propagation method.

Abstract: An image processing system includes a generating unit and a storing unit. The generating unit determines a subject included in a wide-angle image and generate a partial image including the subject from the wide-angle image. The storing unit stores the partial image in association with the wide-angle image from which the partial image is extracted.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a learning device includes a noise generation unit, a decoding unit, a generation unit, and a learning unit. The noise generation unit outputs a second code word which corresponds to a first code word to which noise has been added. The decoding unit decodes the second code word and outputs a third code word. The generation unit generates learning data for learning a weight in message passing decoding in which the weight and a message to be transmitted are multiplied, based on whether or not decoding of the second code word into the third code word has been successful. The learning unit determines a value for the weight in the message passing decoding by using the learning data.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.