Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.

Abstract: A display device includes a display unit that reproduces motion image data, and provides mode information indicating a mode of reproduction of the motion image data; a storage unit that stores a criterion for aborting a reproduction of motion image data reproduced by the display unit according to a mode of reproduction of motion image data; and a determination unit that, in response to a request for aborting a reproduction of motion image data reproduced by the display unit, determines whether to abort the reproduction of the motion image data based on a criterion for aborting a reproduction of motion image data stored in the storage unit according to the mode of reproduction indicated by the mode information.

Abstract: A display apparatus connected to a content server via a network, includes a content acquisition unit that acquires content with an input format; an input format detection unit that detects an input format of content to be acquired; a storage unit that stores information on the content server connected to the display apparatus; a server search unit that searches for a content server in the network; and a server connection unit that, upon the input format detection unit detecting that the input format of the content to be acquired is an input format of content acquired from a content server, connects to at least one of a content server specified by the information stored in the storage unit and a content server searched for and detected by the server search unit.

Abstract: According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.

Abstract: According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

Abstract: According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell unit, an encoding circuit that generates a first parity and a second parity for data, and a decoding circuit that performs error correction by using the data, the first parity, and the second parity, the first parity is generated by using a first generation polynomial for the data, the second parity is generated by using a second generation polynomial for the input data and the first parity, the second generation polynomial is selected based on the first generation polynomial, the data and the first parity is output to the outside, and the second parity is not output to the outside.

Abstract: Disclosed is an image processing apparatus having a function to cooperatively output, via a cooperative image processing apparatus, document data, including a data sending unit that sends to the cooperative image processing apparatus the document data to be output, for which the total limited number of output times is set, with output setting information including an allocated number of output times for the document data individually allocated for the cooperative image processing apparatus; and a number updating unit that updates the total limited number of output times set for the document data based on the allocated number of output times by subtracting the allocated number of output times from the total limited number of output times, when the data sending unit sends the document data with the output setting information to the cooperative image processing apparatus.

Abstract: According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s<t) symbols on read data, and a second error correction decoding units that perform an error correction decoding process of correcting t symbols on read data from which an error is detected after the error correction decoding process of correcting s symbols.

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract: An image processing apparatus utilization system includes image processing apparatuses; an apparatus search unit configured to search for the image processing apparatuses; a capability information obtaining unit configured to obtain scanning capability information from the image processing apparatuses; a delivery setting receiving unit configured to receive a delivery setting for a first image processing apparatus; a first scenario generation unit configured to generate a scenario including the scanning capability information and the delivery setting for the first image processing apparatus; a second scenario generation unit configured to generate scenarios for second image processing apparatuses based on the scenario for the first image processing apparatus; a scenario storing unit configured to store the scenarios generated by the first and second scenario generation units; and an image delivery unit configured to send image data received from one of the image processing apparatuses according to the deliver

Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities.

Abstract: An image forming apparatus connected to an image forming system in which a plurality of image forming apparatuses is linked. The image forming apparatus comprises: a user environment information acquiring unit that acquires user environment information; a user environment information reflecting unit that generates the screen representing the settings by using the user environment information; a capability acquiring unit that acquires capability information representing capabilities; a settability determining unit that determines the settability of various settings; a display control unit that is a unit displaying the screen on the display unit and further displays the screen that represents a determination result of the settability determining unit on the display unit; a search unit that searches for a first image forming apparatus; and a search result output unit that further displays the screen representing a search result of the search unit on the display unit through the display control unit.

Abstract: An image forming apparatus including an acquisition unit configured to acquire a plurality of combinations of document reading settings and delivery destination information of image data from a storage device configured to store the plurality of combinations, a reception unit configured to display the plurality of combinations acquired by the acquisition unit and receive a selection of the plurality of combinations by a user, a duplication identification unit configured to determine, upon the reception unit receiving the selection, whether the selected plurality of combinations contain duplicated delivery destination information, and a control unit configured to control, upon the duplication identification unit determining that the selected plurality of combinations selected contain the duplicated delivery destination information, a transmission of image data such that the image data is transmitted once to a delivery destination corresponding to the duplicated delivery destination information.

Abstract: According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i?1)-th parities.

Abstract: The present invention provides a novel communications apparatus that includes a plurality of wired LAN functions and wireless LAN functions and facilitates determining which network interface is to be enabled more flexibly. The communications apparatus of this invention switches a plurality of wired LAN functions and wireless LAN functions and includes a network interface control unit that enables and disables wired LAN and wireless LAN, a wired LAN communication availability status acquisition unit that detects that there is a change in the status of communication availability of wired LAN and acquires the status of communication availability of wired LAN, and a network interface determining unit that enables only one network interface from communication availability status of wired LAN acquired by the wired LAN communication availability status acquisition unit and a plurality of operating states of the apparatus.

Abstract: According to an embodiment, a semiconductor memory device includes a nonvolatile memory; an input/output control unit to control input/output of data to/from the nonvolatile memory; an address translation table that associates first address information specifying a logical recording position of user data stored in the nonvolatile memory with second address information indicating a physical recording position in the nonvolatile memory; a translating unit to translate the first address information to the second address information according to the table; and a generating unit to generate redundant data for checking whether there is error in the user data and the first address information used as one data piece. The input/output control unit records, as data set, the user data, the first address information, and the redundant data, which are used as one data set, in the physical recording position in the nonvolatile memory indicated by the second address information.

Abstract: According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.