Patents by Inventor Osamu Uehara

Osamu Uehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100230234
    Abstract: A deformed-coin detector accurately detecting a deformed coin without being affected by a variation in transporting speed of a coin. A coin transported along a coin transporting face comes into contact with detecting elements of coin-thickness detecting bodies, the detecting elements move by a distance corresponding to the dimension of the coin in its thickness direction and simultaneously, light shielding portions of the coin-thickness detecting bodies move. A light detecting portion detects a light shielding amount that varies due to movement of the light shielding portions. A coin denomination determining unit determines a denomination of the coin transported along the coin transporting face and reads a reference light-shielding amount pre-stored in a reference light shielding amount storing unit regarding the denomination.
    Type: Application
    Filed: July 21, 2006
    Publication date: September 16, 2010
    Applicant: Glory Ltd.
    Inventors: Takashi Ishimatsu, Satoru Katori, Kazuyuki Shimizu, Yasushi Hiraoka, Osamu Uehara
  • Patent number: 7777472
    Abstract: A current detector circuit detects a current supplied to a load and generates as a detection result a voltage corresponding to the detected current. A first p-channel transistor has a source connected to a power supply and a gate connected to a ground, and is configured to allow the passage therethrough of a current that is 1/N of a current flowing through a transistor which drives the load. A second p-channel transistor has a source connected to a drain of the first p-channel transistor, and a third p-channel transistor is connected to the load. A voltage mirror circuit has first and second terminals connected to respective drains of the second and third p-channel transistors. A n-channel transistor has a drain connected to the drain of the first p-channel transistor and outputs a source voltage as the detection result of the current detector circuit.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: August 17, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Osamu Uehara
  • Patent number: 7766229
    Abstract: A bill and coin processing system including a bill and coin processing apparatus having: an interface unit capable of exchanging information via a communication unit with the point-of-sales terminal machine; a money receiving unit receiving money by way of a price of a commercial product; a discriminating unit discriminating between at least denominations of the bills and coins received from the money receiving unit; a storing/discharging unit stored with the received bills and coins on the basis of a result of the discrimination made by the discriminating unit and capable of discharging the bills and coins by giving a discharge instruction to the bill and coin processing apparatus from the point-of-sales terminal machine; a money discharging unit discharging the bills and coins outside a machine, which have been discharged from the storing/discharging unit; and a control unit controlling the money discharging unit to discharge the bills and coins from the storing/discharging unit on the basis of a discharge
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: August 3, 2010
    Assignee: Glory Ltd.
    Inventors: Osamu Uehara, Takashi Ishimatsu, Kazuyuki Shimizu, Kazuhiro Doi, Koichi Nishida
  • Patent number: 7615973
    Abstract: Provided is an adder in which all of circuits can be constituted by CMOS transistors, a process is simplified, and a chip size can be reduced as compared with a conventional art. The adder according to the present invention includes: a first VI converter and a second VI converter that allow a current corresponding to an input voltage to flow therein; and a current addition resistor having one end commonly connected to output terminals of the first VI converter and the second VI converter and another end grounded, which is adjustable in a resistance value.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 10, 2009
    Assignee: Seiko Instruments Inc.
    Inventor: Osamu Uehara
  • Patent number: 7599052
    Abstract: A defect marking device includes a flaw inspection device which has a plurality of light-receiving parts that identify reflected lights coming from an inspection plane of a metal strip under two or more of optical conditions different from each other; a signal processing section that judges the presence/absence of surface flaw on the inspection plane based on a combination of reflected light components identified under these optical conditions different from each other; and a marking device which applies marking that indicates information relating to the flaw on the surface of the metal strip.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: October 6, 2009
    Assignee: NKK Corporation
    Inventors: Mitsuaki Uesugi, Shoji Yoshikawa, Masaichi Inomata, Tsutomu Kawamura, Takahiko Oshige, Hiroyuki Sugiura, Akira Kazama, Tsuneo Suyama, Yasuo Kushida, Shuichi Harada, Hajime Tanaka, Osamu Uehara, Shuji Kaneto, Masahiro Iwabuchi, Kozo Harada, Shinichi Tomonaga, Shigemi Fukuda
  • Publication number: 20090167410
    Abstract: Provided is a power supply switching circuit capable of efficiently supplying a desired voltage among a plurality of voltages to a load. In the case of a P-type semiconductor substrate, N-type MOS transistors are provided between a load and an AC adapter and between the load and a battery, and hence no parasitic diode exists between the load and the AC adapter or the battery, resulting in no current path due to the parasitic diode. Thus, when the AC adapter and the battery are connected to the power supply switching circuit, the N-type MOS transistor is turned off, whereby the current path between the battery and the load is cut off completely and the N-type MOS transistor is turned on. Accordingly, the battery cannot supply a voltage to the load while only the AC adapter can supply a voltage to the load.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Inventors: Kiyoshi Yoshikawa, Fumiyasu Utsunomiya, Toshiyuki Tsuzaki, Hiroyuki Masuko, Osamu Uehara, Hiroki Wake, Michiyasu Deguchi
  • Publication number: 20090101468
    Abstract: Provided is a bill and coin processing system having: a bill change discharger constructed as a bill receiving/discharging machine; and a coin change discharger constructed as a coin receiving/discharging machine, wherein a machine dimension of each of the bill change discharger and the coin change discharger is that a width is equal to or smaller than 500 mm, a depth is equal to or smaller than 600 mm, and a height is equal to or smaller than 400 mm. Further provided is a similar bill and coin processing system, wherein money input/output ports of the bill change discharger and of the coin change discharger are disposed in positions, which are 700 mm through 1500 mm in height from a floor surface.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 23, 2009
    Applicant: Glory Ltd.
    Inventors: Osamu Uehara, Kazuhiro Doi, Kazuyuki Shimizu, Koichi Nishida
  • Publication number: 20090101723
    Abstract: A bill and coin processing system including a bill and coin processing apparatus having: an interface unit capable of exchanging information via a communication unit with the point-of-sales terminal machine; a money receiving unit receiving money by way of a price of a commercial product; a discriminating unit discriminating between at least denominations of the bills and coins received from the money receiving unit; a storing/discharging unit stored with the received bills and coins on the basis of a result of the discrimination made by the discriminating unit and capable of discharging the bills and coins by giving a discharge instruction to the bill and coin processing apparatus from the point-of-sales terminal machine; a money discharging unit discharging the bills and coins outside a machine, which have been discharged from the storing/discharging unit; and a control unit controlling the money discharging unit to discharge the bills and coins from the storing/discharging unit on the basis of a discharge
    Type: Application
    Filed: October 22, 2007
    Publication date: April 23, 2009
    Applicant: Glory Ltd.
    Inventors: Osamu Uehara, Takashi Ishimatsu, Kazuyuki Shimizu, Kazuhiro Doi, Koichi Nishida
  • Patent number: 7514988
    Abstract: Provided is a band gap constant-voltage circuit capable of achieving a quick startup time to thereby preventing an output voltage from being stabilized at 0 V due to noise or the like even under the normal condition. The band gap constant-voltage circuit according to the present invention includes: an output voltage detecting circuit for monitoring a voltage at an output terminal; and a current source which has a current value controlled through an output of the output voltage detecting circuit, in which the current source supplies a bipolar transistor constituting a level shifter circuit with a current when the voltage at the output terminal is lower than a predetermined voltage.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 7, 2009
    Assignee: Seiko Instruments Inc.
    Inventor: Osamu Uehara
  • Publication number: 20090086209
    Abstract: A defect marking device includes a flaw inspection device which has a plurality of light-receiving parts that identify reflected lights coming from an inspection plane of a metal strip under two or more of optical conditions different from each other; a signal processing section that judges the presence/absence of surface flaw on the inspection plane based on a combination of reflected light components identified under these optical conditions different from each other; and a marking device which applies marking that indicates information relating to the flaw on the surface of the metal strip.
    Type: Application
    Filed: August 13, 2008
    Publication date: April 2, 2009
    Applicant: NKK Corporation
    Inventors: Mitsuaki Uesugi, Shoji Yoshikawa, Masaichi Inomata, Tsutomu Kawamura, Takahiko Oshige, Hiroyuki Sugiura, Akira Kazama, Tsuneo Suyama, Yasuo Kushida, Shuichi Harada, Hajime Tanaka, Osamu Uehara, Shuji Kaneto, Masahiro Iwabuchi, Kozo Harada, Shinichi Tomonaga, Shigemi Fukuda
  • Publication number: 20080231247
    Abstract: To obtain a switching regulator which, when a load suddenly decreases, suppresses overshoot of output voltage without oscillating the output voltage is provided, even if being a current mode switching regulator, the present invention provides a semiconductor device for a switching regulator for converting input direct current voltage input from a direct current power supply to set direct current output voltage and outputting the output voltage from an output terminal, including: an overvoltage protection circuit for: comparing a target voltage with the output voltage at the output terminal; and making the output terminal in a discharge state when the output voltage exceeds the target voltage.
    Type: Application
    Filed: February 15, 2008
    Publication date: September 25, 2008
    Inventor: Osamu Uehara
  • Publication number: 20080218142
    Abstract: A current detector circuit is completely formed of CMOS transistors, and is simplified in process, and can be reduced in the chip size. The current detector circuit of the present invention generates a sense voltage that corrects a voltage for slope compensation according to a coil current in a current mode switching regulator.
    Type: Application
    Filed: February 15, 2008
    Publication date: September 11, 2008
    Inventor: Osamu Uehara
  • Patent number: 7423744
    Abstract: A defect marking device includes a flaw inspection device which has a plurality of light-receiving parts that identify reflected lights coming from an inspection plane of a metal strip under two or more of optical conditions different from each other; a signal processing section that judges the presence/absence of surface flaw on the inspection plane based on a combination of reflected light components identified under these optical conditions different from each other; and a marking device which applies marking that indicates information relating to the flaw on the surface of the metal strip.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: September 9, 2008
    Assignee: NKK Corporation
    Inventors: Mitsuaki Uesugi, Shoji Yoshikawa, Masaichi Inomata, Tsutomu Kawamura, Takahiko Oshige, Hiroyuki Sugiura, Akira Kazama, Tsuneo Suyama, Yasuo Kushida, Shuichi Harada, Hajime Tanaka, Osamu Uehara, Shuji Kaneto, Masahiro Iwabuchi, Kozo Harada, Shinichi Tomonaga, Shigemi Fukuda
  • Publication number: 20080203988
    Abstract: Provided is an adder in which all of circuits can be constituted by CMOS transistors, a process is simplified, and a chip size can be reduced as compared with a conventional art. The adder according to the present invention includes: a first VI converter and a second VI converter that allow a current corresponding to an input voltage to flow therein; and a current addition resistor having one end commonly connected to output terminals of the first VI converter and the second VI converter and another end grounded, which is adjustable in a resistance value.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 28, 2008
    Inventors: Minoru Horikawa, Osamu Uehara
  • Publication number: 20080078143
    Abstract: The present invention provides a coin-roll storing machine which can reduce the dimension in the width direction and facilitate to ensure the installation space, as compared with those of a type including a plurality of coin-roll storing portions each adapted to put the coin-roll on the bottom face such that the axis of each coin-roll package extends in the horizontal width direction. In one aspect, a coin-roll storing machine 1 includes a storing main body 1a, and three coin-roll drawers 11, 12, 13, respectively provided such that they can be drawn out relative to the storing main body 1a. In the respective coin-roll drawers 11, 12, 13, a plurality of coin-roll storing portion 14 are provided, each for storing coin-roll B, with each axis of the coin-roll B being oriented in the vertical direction.
    Type: Application
    Filed: September 25, 2007
    Publication date: April 3, 2008
    Applicant: Glory, Ltd.
    Inventors: Osamu Uehara, Mikito Imai, Yumiko Imai, Koichi Nishida, Hiroshi Tone
  • Publication number: 20070210856
    Abstract: Provided is a band gap constant-voltage circuit capable of achieving a quick startup time to thereby preventing an output voltage from being stabilized at 0 V due to noise or the like even under the normal condition. The band gap constant-voltage circuit according to the present invention includes: an output voltage detecting circuit for monitoring a voltage at an output terminal; and a current source which has a current value controlled through an output of the output voltage detecting circuit, in which the current source supplies a bipolar transistor constituting a level shifter circuit with a current when the voltage at the output terminal is lower than a predetermined voltage.
    Type: Application
    Filed: February 15, 2007
    Publication date: September 13, 2007
    Inventor: Osamu Uehara
  • Publication number: 20070181952
    Abstract: Provided is a band gap constant-voltage circuit which is configured by combining a PMOS transistor, an NMOS transistor, a bipolar transistor, and a resistor, and is capable of preventing an output voltage from being stabilized at 0 V immediately after power supply fluctuation. According to the band gap constant-voltage circuit of the present invention, the back-gates of two p-type transistors (P112 and P113) constituting a differential amplifier are each connected to a node 11 which is a power source terminal on the positive side of the differential amplifier, and a level shifter circuit is connected to the gate of each of the transistors (P112 and P113).
    Type: Application
    Filed: January 19, 2007
    Publication date: August 9, 2007
    Inventor: Osamu Uehara
  • Patent number: 7248366
    Abstract: The defect marking method comprises the steps of: installing a surface defect tester to detect surface flaw and a marker device to apply marking at defect position, in a continuous processing line of steel sheet; detecting the surface flaw on the steel sheet using the surface defect tester; determining defect name, defect grade, defect length, and defect position in the width direction of the steel sheet, on the basis of thus detected flaw information, further identifying the defect in terms of harmful defect, injudgicable defect, and harmless defect; applying tracking of the defect position for each of the harmful defect and the injudgicable defect; and applying marking to the defect position. The defect marking device comprises a defect inspection means having plurality of light-receiving parts and a signal processing section, and a marking means.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: July 24, 2007
    Assignee: NKK Corporation
    Inventors: Mitsuaki Uesugi, Shoji Yoshikawa, Masaichi Inomata, Tsutomu Kawamura, Takahiko Oshige, Hiroyuki Sugiura, Akira Kazama, Tsuneo Suyama, Yasuo Kushida, Shuichi Harada, Hajime Tanaka, Osamu Uehara, Shuji Kaneto, Masahiro Iwabuchi, Kozo Harada, Shinichi Tomonaga, Shigemi Fukuda
  • Publication number: 20070052964
    Abstract: A defect marking device includes a flaw inspection device which has a plurality of light-receiving parts that identify reflected lights coming from an inspection plane of a metal strip under two or more of optical conditions different from each other; a signal processing section that judges the presence/absence of surface flaw on the inspection plane based on a combination of reflected light components identified under these optical conditions different from each other; and a marking device which applies marking that indicates information relating to the flaw on the surface of the metal strip.
    Type: Application
    Filed: October 24, 2006
    Publication date: March 8, 2007
    Applicant: NKK Corporation
    Inventors: Mitsuaki Uesugi, Shoji Yoshikawa, Masaichi Inomata, Tsutomu Kawamura, Takahiko Oshige, Hiroyuki Sugiura, Akira Kazama, Tsuneo Suyama, Yasuo Kushida, Shuichi Harada, Hajime Tanaka, Osamu Uehara, Shuji Kaneto, Masahiro Iwabuchi, Kozo Harada, Shinichi Tomonaga, Shigemi Fukuda
  • Patent number: 6815773
    Abstract: A semiconductor device is provided in which: a parasitic capacitance between a drain and a supporting substrate is reduced; and a high electric field generated in the vicinity of the drain is relaxed and which has a high withstand voltage. A MOS transistor according to the present invention includes: a supporting substrate region in an SOT substrate; a buried insulating film formed on the supporting substrate region; a channel region formed on the buried insulating film; and first and second offset regions that are formed on the buried insulating film so as to be adjacent to the channel region on both sides thereof, and further includes an impurity diffusion region formed in a portion positioned below the second offset region in the supporting substrate region.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: November 9, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Osamu Uehara, Jun Osanai