Abstract: A semiconductor device is provided in which: a parasitic capacitance between a drain and a supporting substrate is reduced; and a high electric field generated in the vicinity of the drain is relaxed and which has a high withstand voltage. A MOS transistor according to the present invention includes: a supporting substrate region in an SOT substrate; a buried insulating film formed on the supporting substrate region; a channel region formed on the buried insulating film; and first and second offset regions that are formed on the buried insulating film so as to be adjacent to the channel region on both sides thereof, and further includes an impurity diffusion region formed in a portion positioned below the second offset region in the supporting substrate region.

Abstract: The defect marking method comprises the steps of: installing a surface defect tester to detect surface flaw and a marker device to apply marking at defect position, in a continuous processing line of steel sheet; detecting the surface flaw on the steel sheet using the surface defect tester; determining defect name, defect grade, defect length, and defect position in the width direction of the steel sheet, on the basis of thus detected flaw information, further identifying the defect in terms of harmful defect, injudgicable defect, and harmless defect; applying tracking of the defect position for each of the harmful defect and the injudgicable defect; and applying marking to the defect position. The defect marking device comprises a defect inspection means having plurality of light-receiving parts and a signal processing section, and a marking means.

Abstract: A method forwarding a semiconductor device that is excellent in bonding strength of bumps with respective protruded electrodes and having high reliability. A wiring pattern 28 to be connected to an electrode 22 of a semiconductor chip 20 is formed on an insulting film 23 formed on the semiconductor chip 20 in which the electrode 20 is formed. Protruded electrodes 32 are formed on the wiring pattern 28. The wiring pattern 28 is covered with a protective film 36, and a bump 38 for external connection is formed on the end portion of each of the protruded electrodes 32 exposed from the protective film 36. The bump 38 is formed in such a manner that the bump is bonded to the at least entire end face of each of the protruded electrodes 32.

Abstract: A semiconductor device excellent in bonding strength of bumps with respective protruded electrodes and having high reliability wherein a wiring pattern 28 to be connected to an electrode 22 of a semiconductor chip 20 is formed on an insulting film 23 formed on the semiconductor chip 20 in which the electrode 20 is formed, protruded electrodes 32 are formed on the wiring pattern 28, the wiring pattern 28 is covered with a protective film 36, and a bump 38 for external connection is formed on the end portion of each of the protruded electrodes 32 exposed from the protective film 36, the bump 38 is formed in such a manner that the bump is bonded to the at least entire end face of each of the protruded electrodes 32.

Abstract: The invention provides a process and an apparatus for laminating a film 1 and a film 2 by thermocompression bonding.When the film 1 and the film 2 are laminated by thermocompressing bonding with a heat roll 3 and a pressure roll 4, the film 1 is guided onto the heat roll 3 via a feed angle adjusting roll 5 for automatically adjusting the distance of contact of the film with the heat roll 3, and/or the laminate film formed by thermocompression bonding is released from the heat roll 3 by being passed over a discharge angle adjusting roll 8 for automatically adjusting the distance of contact of the laminate film with the heat roll.