Patents by Inventor Osamu Usuda

Osamu Usuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7633153
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: December 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Patent number: 7514783
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: April 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20090001135
    Abstract: A semiconductor manufacturing apparatus operable to simultaneously apply supersonic vibration to two bonding sites located at different heights to simultaneously perform bonding of the two bonding sites, the apparatus includes: a cylindrical body; a first protrusion provided on an outer peripheral surface of the cylindrical body and receiving supersonic vibration propagated through the cylindrical body; and a second protrusion provided on the outer peripheral surface of the cylindrical body and receiving supersonic vibration propagated through the cylindrical body. A distance between an axial center of the cylindrical body and the tip of the first protrusion is generally equal to the distance between the axial center of the cylindrical body and the tip of the second protrusion. A tip surface of the first protrusion and a tip surface of the second protrusion are on different planes, respectively.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Kishimoto, Osamu Usuda
  • Patent number: 7332804
    Abstract: A semiconductor device and manufacturing the semiconductor device are described. There is provided a method of manufacturing a semiconductor device including, disposing a lead frame inside an outer lead so as to couple between a coupling portion and a coupling acceptance portion, the lead frame including a chip mounting portion and the coupling acceptance portion, the outer lead including a frame portion with outer terminal portions and the coupling portion, disposing a semiconductor chip on the chip mounting portion, connecting between the outer terminal portions and the semiconductor chip with a plurality of wires or leads, sealing the outer terminal portion, the lead frame disposed the semiconductor chip on and the wires or the leads by a mold resin, cutting off the outer terminal portions from the outer lead, and uncoupling the coupling portion from the coupling acceptance portion.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: February 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eitaro Miyake, Yoshihiko Tojo, Osamu Usuda
  • Publication number: 20070257376
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 8, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20070257708
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 8, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Patent number: 7292424
    Abstract: An object of the present invention is to provide an arcing horn system having a highly efficient dynamic current shutoff property including a dynamic current shutoff capability, for example, enough for the short circuit fault and other object thereof is to provide an arcing horn system capable of repeatedly maintaining the good dynamic current shutoff capability.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: November 6, 2007
    Assignees: Central Research Institute of Electric Power Industry, Kansai Electric Power Co., Inc., Tokyo Electric Power Co., Inc., Nippon Katan Co., Ltd.
    Inventors: Kazuhiko Takasu, Takashi Chino, Osamu Usuda, Toshio Watanabe, Tomoyasu Hasegawa, Kazuhiko Shimoda, Satoru Doi, Takehiko Kikuchi, Katsuyuki Urasawa, Hiroaki Kanatsuji, Yoshihiko Ota, Hiroki Sakamoto, Ryoji Matsushita
  • Publication number: 20060213872
    Abstract: An object of the present invention is to provide an arcing horn system having a highly efficient dynamic current shutoff property including a dynamic current shutoff capability, for example, enough for the short circuit fault and other object thereof is to provide an arcing horn system capable of repeatedly maintaining the good dynamic current shutoff capability. In an arcing horn system, an insulative tube 21 for surrounding a front end side of an arcing horn 11, 12 is provided and an air vent 21a communicating from a front end portion of the arcing horn 11, 12 to a front end surface of the insulative tube 21 is formed on the insulative tube 21, so that the arc jet is blown off from the air vent 21a upon the flashover in accordance with the thunder stroke. The insulative tube 21 is made of a polyamide resin. A cap 30 for covering the front end side of the insulative tube 21 is disposed so as to prevent the intrusion of the rain water into the air vent 21a.
    Type: Application
    Filed: September 13, 2002
    Publication date: September 28, 2006
    Inventors: Kazuhiko Takasu, Takashi Chino, Osamu Usuda, Toshio Watanabe, Tomoyasu Hasegawa, Kazuhiko Shimoda, Satoru Doi, Takehiko Kikuchi, Katsuyuki Urasawa, Hiroaki Kanatsuji, Yoshihiko Ota, Hiroki Sakamoto, Ryoji Matsushita
  • Publication number: 20060055432
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 16, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20050285240
    Abstract: A semiconductor device and manufacturing the semiconductor device are described. There is provided a method of manufacturing a semiconductor device including, disposing a lead frame inside an outer lead so as to couple between a coupling portion and a coupling acceptance portion, the lead frame including a chip mounting portion and the coupling acceptance portion, the outer lead including a frame portion with outer terminal portions and the coupling portion, disposing a semiconductor chip on the chip mounting portion, connecting between the outer terminal portions and the semiconductor chip with a plurality of wires or leads, sealing the outer terminal portion, the lead frame disposed the semiconductor chip on and the wires or the leads by a mold resin, cutting off the outer terminal portions from the outer lead, and uncoupling the coupling portion from the coupling acceptance portion.
    Type: Application
    Filed: June 28, 2005
    Publication date: December 29, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eitaro Miyake, Yoshihiko Tojo, Osamu Usuda
  • Patent number: 5060051
    Abstract: In a semiconductor device in which copper or copper alloy bonding wire is bonded to an electrode pad on a semiconductor element, the electrode pad is formed of a first metal layer ohmically contacting the semiconductor element, a second metal layer hard enough not to be deformed at wire bonding step, and a third metal layer for bonding a copper wire, to suppress variation in the electric characteristics of a bonding portion and the production of stain in the semiconductor element at wire bonding step.
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: October 22, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Usuda
  • Patent number: 4732313
    Abstract: A lead frame is conveyed along a convey direction in a convey path filled with a reducing gas. A semiconductor pellet is placed on the lead frame at a die bonding portion. A bonding wire made of copper or a copper alloy is supplied to the next wire bonding portion. The lower end of the bonding wire is melted with an oxyhydrogen torch surrounded by an air curtain, thereby forming a ball. The bonding wire is guided into the convey path by a capillary. The ball is thermocompressed to an electrode pad of the semiconductor pellet. The other end of the bonding wire is fused and thermocompressed against the outer lead of the lead frame at a postbonding portion. The bonding wire is thus looped between the semiconductor pellet and the outer lead.
    Type: Grant
    Filed: July 26, 1985
    Date of Patent: March 22, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mituo Kobayashi, Osamu Usuda, Yoshihiko Sano, Koichiro Atsumi
  • Patent number: D508682
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Yamada, Kazuhiko Kurahashi, Toshihisa Inoue, Taizo Tomioka, Kazuo Shimokawa, Yoshiki Endo, Masahiro Urase, Osamu Usuda
  • Patent number: D521952
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Yamada, Kazuhiko Kurahashi, Toshihisa Inoue, Taizo Tomioka, Kazuo Shimokawa, Yoshiki Endo, Masahiro Urase, Osamu Usuda