Abstract: The present invention discloses a cryptographic method using redundant bits and an adaptive clock frequency, which adds redundant bits and modifies clock frequency to change the contents and transmission rate of the bit sequence to encrypt data. The present invention can combine with the existing security mechanism or cryptographic algorithm, such as AES (Advanced Encryption Standard) or DES (Data Encryption Standard), to achieve a multi-fold security function. Thereby, the present invention can apply to various communication devices to increase the immunity against attacks, promote information security and protect personal privacy.

Abstract: A variable length decoder and its decoding method utilizing a reordered index decoding look-up-table, and that is utilized to incorporate a plurality of decoding LUT's into a single reordered index decoding LUT for use in decoding by making use of the output correlation rule obtained through integrating a plurality of decoding LUT's. Thus, when proceeding with the variable length decodings, the multiplexer has only to select the correct reordered index value from among a plurality of reordered index values as based on the previous decoding results, and then find out the corresponding remapping index value and compensation value, thus searching and obtaining the corresponding reordered index output result in the reordered index decoding LUT through utilizing the remapping index value, hereby obtaining the output result through proceeding with the operations required by making use of the compensation value.

Abstract: A method of test includes the steps of preparing a sensing platform having an emitting electrode mounted at on one side thereof and a receiving electrode mounted on the other side thereof, wherein the sensing platform defines a sensing zone located between the emitting and receiving electrodes; placing a specimen on the sensing zone; emitting a surface acoustic wave from the emitting electrode, wherein the surface acoustic wave passes through the sensing zone and the specimen and then is received by the receiving electrode to be changed for its speed and phase by the change of material property of the specimen; and identifying the material property of the specimen according to the changed speed and phase of the surface acoustic wave to further infer the physical property of the specimen. In light of the steps, the surface acoustic wave can be employed for detection of the physical property of the specimen.

Abstract: A method for reducing memory resource utilization is disclosed, applied to simplify address space of a table. Values stored in address fields of an original table are analyzed to determine whether logical relationship is detected between the values. If the logical relationship is detected, the values stored in the original table are classified to multiple base values and corresponding reduced values to generate a transformation table. Values with the same logical relationship for base values and the corresponding reduced values are stored in a new and equivalent address field of a reduction table.

Abstract: An integrated transformation apparatus is provided. The apparatus includes a first multiplexer, a second multiplexer, and a transformation unit. The first multiplexer retrieves point data from columns or rows of a multi-dimensional matrix and input data. The second multiplexer retrieves transformation coefficients corresponding to the point data. The transformation unit transforms data blocks of the multi-dimensional matrix to a plurality of sub data blocks according to the input data, the point data, and the transformation coefficients.

Abstract: A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.

Abstract: The invention provides a multi-phase oscillator includes a delay loop buffer and plurality of oscillators. The delay loop buffer has N delay units. The oscillator can be a single phase oscillator, a 180° phase difference oscillator or a multiple phase difference oscillator. The N delay units are used to constitute a configuration having 360° phase shift where each delay unit has the same delay time and phase shift. Furthermore, a 180° phase difference oscillator composed of a plurality of inverters and a regenerator can be applied in the multi-phase oscillator.

Abstract: The design methods and apparatuses of photodiodes with adaptive structures to achieve smooth and wavelength-selective responses are proposed. By using the adequate sizes of the photo-sensing areas and gains of the back-end amplifiers towards the different photo-responses of multiple photodiodes, the photo-responses from these photodiodes are summed together to yield the uniform distribution of the total photo-responses. Based on the physical characteristics of the process parameters, the equation of the photo-responses for the PN junction is derived to find the optimized values of the process parameters for increasing the photo-response and achieving the peak value of the photo-responses at a specific wavelength. The photodiode with multiple PN junctions and multiple switches is designed to achieve multiple photo-responses in a single photodiode. By using the switches to turn off the unused PN junctions, the selected PN junctions can generate the required photo-responses.

Abstract: A signal-processing method for performing a coordinate transformation operation and a quantization operation on an input data to obtain quantization outputs, and a signal-processing device therefor. A search strategy based on the characteristic of the input data is established. By using the search strategy, the End of Block (EOB) is predicted and the calculation structure is determined by the predicted EOB.

Abstract: The present invention provides an adaptive filter and a learning method therefor to eliminate real output signals generated by input signals and an environment signal response. The adaptive filter receives the input signals from an input signal source and generates estimated output signals according to an filter coefficients and the input signals. The first step of the learning method is storing the input signals and the real output signals within a past time period. Then, a predictive input signal and a predictive output signal are generated according to the input signals and the real output signals in the memories, respectively. Finally, the filter coefficients is updated according to the predictive input signal, the predictive output signal, one of the input, signals and one of the real output signals, causing the estimated signals to approximate the real output signals.

Abstract: A multi-phase oscillator and a multi-phase oscillation signal generation method. Wherein, the multi-phase oscillator comprises a delay loop buffer and plurality of oscillators. The delay loop buffer has N delay units. The oscillator can be a single phase oscillator, a 180° phase difference oscillator or a multiple phase difference oscillator. The N delay units are used to constitute a configuration having 360° phase shift where each delay unit has the same delay time and phase shift. Hence, the oscillation signals generated by the oscillators have a 360°/N phase difference that is not variable. Furthermore, the present invention also provides a 180° phase difference oscillator that can be applied in the multi-phase oscillator. Wherein, the 180° phase difference oscillator is composed of a plurality of inverters and a regenerator.

Abstract: A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.

Abstract: A wide-range and low power consumption voltage-controlled oscillator according to the invention includes a logic control circuit, a parallel series controllable inverter bank and a voltage control load. The logic control circuit consists of a plurality of logic gates for receiving a selecting signal from an external device and then transmitting a control signal. The parallel series controllable inverter bank consists of a plurality of series controllable inverter banks electrically connected in parallel for receiving the control signal and outputting an oscillation signal, wherein the control signal is used to control the number of the series controllable inverter banks electrically connected in parallel. The voltage control load is electrically connected between the parallel series controllable inverter bank and ground for serving as a load of the parallel series controllable inverter bank.