Patents by Inventor Oscar Buset

Oscar Buset has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7155697
    Abstract: A method for routing of some embodiments defines global routes for nets in an arbitrary region of a circuit layout in which each net has a set of pins. The method uses a first set of lines of measure the length of the global routes, a second set of lines to measure congestion of the global routes, and a third set of lines to partition the arbitrary region into a first set of sub-regions. For each net, the method identifies a global route that connects a group of first-set sub-regions that contain the net's set of pins.
    Type: Grant
    Filed: January 13, 2002
    Date of Patent: December 26, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques, Andrew Caldwell, Jonathan Frankle
  • Patent number: 7096448
    Abstract: Some embodiments provide a method of routing nets within a region of an integrated-circuit (“IC”) layout. The method uses a first set of lines to partition the IC region into a plurality of sub-regions. In addition, the method uses a second set of lines to measure congestion of routes for the nets within the IC region. According to this method, at least some of the lines in the second set are different from the lines in the first set.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: August 22, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Heng-Yi Chao
  • Patent number: 7073150
    Abstract: Some embodiments provide a hierarchical routing method that uses diagonal routes. This method routes a net within a particular region of an integrated circuit (“IC”) layout. This net includes several pins in the region. The method initially partitions the particular IC region into a first set of sub-regions. It then identifies a first route that connects a group of first-set sub-regions that contain the net's pins. The identified first route has an edge that is at least partially diagonal. The method next partitions the first-set sub-regions into a second set of smaller sub-regions. It then propagates the first route into the second-set sub-regions.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: July 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 7013450
    Abstract: Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1) for each particular edge, identifies an edge-intersect cost based on a set of potential routes for the nets that intersect the particular edge, and (2) selects routes for the nets based on the computed edge-intersect costs. A potential route for a particular net traverses the set of sub-regions that contain the particular net's set of pins. Also, different embodiments identify different edge-intersect costs.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: March 14, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 7003754
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: February 21, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques
  • Patent number: 6957410
    Abstract: Some embodiments provide a method of routing nets in a region of an integrated-circuit layout. This method initially identifies a characteristic of the region, and then selects a wiring model from a set of wiring models, based on the identified characteristic. Each wiring models specifies a set of routing directions. The method then routes the nets based on the selected wiring model.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: October 18, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6952815
    Abstract: Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1) for each particular net and each particular edge, identifies an edge-intersect probability that specifies the probability that a set of potential routes for the particular net will intersect the particular edge, and (2) uses the identified edge-intersect probabilities to identify routes for the nets. A potential route for a particular net traverses the set of sub-regions that contain the particular net's set of pins. In other embodiments, the method partitions the region into several sub-regions that have a number of paths between them.
    Type: Grant
    Filed: January 13, 2002
    Date of Patent: October 4, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6931616
    Abstract: A routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: August 16, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques
  • Patent number: 6915501
    Abstract: Some embodiments provide an LP method that identities routes. In some embodiments, this method is used by a router that defines routes for nets within a region of a design layout. Each net has a set of pins in the region. The method partitions the region into a set or sub-regions. For each particular net, the method identifies a set or route. Each route for a net traverses the sub-regions that contain the net's pins. Each route includes a set of route edge, and each route edge connects two sub-regions. Also, some of the identified routes have route edges that are at least partially diagonal. The method formulates a linear-programming (“LP”) problem based on the identified sets of routes for the nets. The method then solves the LP problem to identify one route for each net. In some embodiments, the formulated LP problem is an integer-linear-programming (“ILP”) problem, and solving the ILP problem returns integer solutions that specify one route for each net.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: July 5, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6883154
    Abstract: Some embodiments provide an LP method that identifies route propagations. In some embodiments, this method is used by a router that hierarchically defines routes for nets within a region of a design layout. The router (1) partitions the region into a first set of sub-regions, and (2) for each particular net, identifies a route that traverses a set of the first-set sub-regions. In some embodiments, the invention's method partitions the first set of sub-regions into a second set of smaller sub-regions. It then identifies a plurality of propagation possibilities for propagating each route into the second set of smaller sub-regions of the first set sub-regions. The method next formulates a linear-programming (“LP”) problem based on the identified propagation possibilities. The method then solves the LP problem.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: April 19, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6745379
    Abstract: Some embodiments provide a hierarchical method of routing nets within a particular region of a circuit layout. Each net has a set of pins. The method initially partitions the particular region into a first set of sub-regions. For each net, the method identifies a first route that connects a group of first-set sub-regions containing the first net's pins; where some of the routes have at least one route-edge that is at least partially diagonal. The method then partitions the sub-regions into a second set of smaller sub-regions. For a first net, the method identifies a propagation of the first-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions. It then adjusts the congestion between the second set sub-regions based on the identified propagation. For a second net, the method then identifies a propagation of the second-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions.
    Type: Grant
    Filed: January 13, 2002
    Date of Patent: June 1, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6738960
    Abstract: Some embodiments provide a method of producing sub-optimal routes for a net having a set of pins in a region of an integrated-circuit (“IC”) layout. In some embodiments, such a method is used for a router that partitions the region into a plurality of sub-regions. This method initially identifies a first set of sub-regions that contain the net's pins. It then obtains a second set of sub-regions by adding a third set of sub-regions to the first set of sub-regions. Each sub-region in the third set does not contain any pins of the net. For the second set of sub-regions, the method then identifies a first set of routes, where each route traverses the sub-regions in the second set.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: May 18, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Yang-Trung Lin
  • Publication number: 20030088845
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Application
    Filed: January 13, 2002
    Publication date: May 8, 2003
    Inventors: Steven Teig, Oscar Buset
  • Publication number: 20030079193
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Application
    Filed: December 7, 2001
    Publication date: April 24, 2003
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques
  • Publication number: 20030066043
    Abstract: Some embodiments of the invention provide a method for defining routes for nets in a region of a circuit layout. This method uses a first set of lines to measure length of routes, and uses a second set of lines to measure congestion of routes.
    Type: Application
    Filed: January 13, 2002
    Publication date: April 3, 2003
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques, Andrew Caldwell, Jonathan Frankle
  • Publication number: 20030066044
    Abstract: Some embodiments provide a hierarchical method of routing nets within a particular region of a circuit layout. Each net has a set of pins. The method initially partitions the particular region into a first set of sub-regions. For each net, the method identifies a first route that connects a group of first-set sub-regions containing the first net's pins; where some of the routes have at least one route-edge that is at least partially diagonal. The method then partitions the sub-regions into a second set of smaller sub-regions. For a first net, the method identifies a propagation of the first-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions. It then adjusts the congestion between the second set sub-regions based on the identified propagation. For a second net, the method then identifies a propagation of the second-net's first route into the second-set sub-regions based on congestion between the second-set sub-regions.
    Type: Application
    Filed: January 13, 2002
    Publication date: April 3, 2003
    Inventors: Steven Teig, Oscar Buset
  • Publication number: 20030066042
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Application
    Filed: January 5, 2002
    Publication date: April 3, 2003
    Inventors: Steven Teig, Oscar Buset, Etienne Jacques
  • Publication number: 20030056187
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Application
    Filed: January 14, 2002
    Publication date: March 20, 2003
    Inventors: Steven Teig, Oscar Buset
  • Publication number: 20030043827
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Application
    Filed: January 5, 2002
    Publication date: March 6, 2003
    Inventors: Steven Teig, Oscar Buset
  • Publication number: 20030023943
    Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
    Type: Application
    Filed: January 5, 2002
    Publication date: January 30, 2003
    Inventors: Steven Teig, Oscar Buset, Yang-Trung Lin