Abstract: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

Abstract: A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.

Abstract: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.

Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.

Abstract: A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip.

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays.

Abstract: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M1) and extending in the first direction. The first metal line and the second metal line substantially vertically overlap the first conductive line and the second conductive line, respectively. The first metal line and the second metal line form two capacitor electrodes of a capacitor.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a frequency detector coupled with a logic circuit; a supply voltage regulator coupled with the frequency detector and designed to provide an adaptive voltage supply to the logic circuit based on a frequency error from the frequency detector; and a substrate bias regulator coupled with the frequency detector and designed to provide an adaptive body bias voltage to the logic circuit based on the frequency error.