Abstract: A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.

Abstract: A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

Abstract: Asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl).

Abstract: A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.

Abstract: A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

Abstract: An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.

Abstract: A method and memory circuit comprising a plurality of cells accessible by word lines and bit lines is described, wherein each cell includes a group of six transistors adapted to both store a bit inserted into the cell during a write operation and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell, wherein the word lines and bit lines of the memory are divided into sections assigned to groups of equal numbers of cells, wherein said sections are individually accessible for read or write operations such that one cell of a group can be read simultaneously while writing another cell of the group.

Abstract: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

Abstract: Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.

Abstract: Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.

Abstract: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

Abstract: A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

Abstract: A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Abstract: A virtual two-port memory structure with fast write-thru operation is proposed. The virtual two-port memory structure employs a single-port memory cell (200). Means for comparing (260) compare a read address AR with a write address AW and means (270) for writing data from the data input terminal (250) into the cell (200) are bypassing said data to the data output terminal (280) as well, such that a write-thru operation is enabled if the read address AR matches the write address AW. The data just written into the cell are immediately available as read data within the same cycle. The multiplex unit used in prior art solutions is no longer necessary, the delay caused by this device is omitted and the advantages of the virtual two-port cell requiring less chip space are maintained.

Abstract: A static memory cell comprising a pair of cross-coupled transistors and a bit line driver/isolation stage configured as an inverter disposed between one node of the cross-coupled transistors and a read-select transistor. The cell is accessed through a bus which includes a read bit line and a write bit line, the word line being divided into a write word line and a read word line.

Abstract: A closed gas-cell cellular material is formed by heat treating a hydrosilicate, especially perlite, at a low temperature and then in the form of grains of a grain size of 5 to 8000 micrometers, feeding these grains through a space at a temperature of 800.degree. C. to 2000.degree. C. for a short residence time at a uniform space load of 0.1 to 500 kg/h. Then the grains are subjected to thermal shock in a thermal shock space connector directly to the feed spacing and heated to 1,000.degree. C. to 3,500.degree. C. The density of the granular material thus produced is 0.12 to 27 g/cm.sup.3 and the weight per volume thereof at 0.01 to 1 kg/liter.

Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register.

Abstract: Glucopyranosyl and oligoglucosidyl derivatives of 4,6-bisdesoxy-4-(4,5,6-trihydroxy-3-hydroxymethylcyclohex-2-en-1-ylamino)- .alpha.-D-glucopyranose, which are inhibitors of glycoside hydrolases of the digestive tract, favorably improve the meat:fat ratio in animals in favor of a higher proportion of meat. A single amino-sugar or a mixture of amino-sugars can be formulated in combination with an edible carrier and fed to animals. A representative embodiment is a pig feedstuff in admixture with O-{4,6-bisdesoxy-4-[lS-(1,4,6/5)-4,5,6-trihydroxy-3-hydroxymethylcyclohex- 2-en-1-ylamino]-.alpha.-D-glucopyranoxyl}-(1.fwdarw.4)-O-.alpha.-D-glucopyr anosyl-(1.fwdarw.4)-D-glucopyranose.