Patents by Inventor Ovadia Abed
Ovadia Abed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11762284Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.Type: GrantFiled: August 3, 2017Date of Patent: September 19, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn
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Patent number: 11669009Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.Type: GrantFiled: August 3, 2017Date of Patent: June 6, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Paras Ajay, Ofodike Ezekoye
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Publication number: 20230116581Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
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Patent number: 11600525Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).Type: GrantFiled: December 21, 2018Date of Patent: March 7, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
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Publication number: 20230042873Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.Type: ApplicationFiled: October 4, 2022Publication date: February 9, 2023Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Vipul Goyal, Michael Cullinan
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Patent number: 11469131Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.Type: GrantFiled: December 22, 2017Date of Patent: October 11, 2022Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Vipul Goyal, Michael Cullinan
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Publication number: 20220229361Abstract: A method and system for configuring ultraviolet (UV)-based nanoimprint lithography (NIL) for roll-to-roll (R2R) processing, which combines the benefits of inexpensive R2R processing with the precise nanoscale patterning afforded by NIL. Furthermore, an R2R fabrication process is used to create nanoscale copper (Cu) metal mesh electrodes on flexible polycarbonate substrates and rigid quartz substrates employing jet-and-flash nanoimprint lithography (J-FIL), linear ion source etching (LIS) and selective electroless Cu metallization (ECu) using a palladium (Pd) seed layer.Type: ApplicationFiled: May 13, 2020Publication date: July 21, 2022Inventors: Sidlgata V. Sreenivasan, Parth Pandya, Shrawan Singhal, Paras Ajay, Ziam Ghaznavi, Ovadia Abed, Michael Watts
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Publication number: 20210389666Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.Type: ApplicationFiled: August 3, 2017Publication date: December 16, 2021Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn
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Publication number: 20210366771Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).Type: ApplicationFiled: December 21, 2018Publication date: November 25, 2021Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
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Publication number: 20210341833Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.Type: ApplicationFiled: August 3, 2017Publication date: November 4, 2021Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Paras Ajay, Ofodike Ezekoye
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Publication number: 20210134640Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.Type: ApplicationFiled: December 22, 2017Publication date: May 6, 2021Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Vipul Goyal, Michael Cullinan
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Publication number: 20200105154Abstract: A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently. The portable system is used for the design and assembly of a prototype tool with all the functionalities or a subset of functionalities present in a master tool used in a small tech factory.Type: ApplicationFiled: May 16, 2018Publication date: April 2, 2020Inventors: Sidlgata V. Sreenivasan, Ovadia Abed, Lawrence R. Dunn, Aseem Sayal, Shrawan Singhal
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Patent number: 10336062Abstract: Systems and methods for precision inkjet printing are disclosed. A method determining an actuation parameter associated with a pressure waveform. Based on the pressure waveform, the method also includes actuating a print head to eject a droplet from a nozzle and acquiring an image of the droplet. The method further includes processing the acquired image to estimate a volume of the droplet and based on the estimated volume of the droplet and a target volume, adjusting the actuation parameter.Type: GrantFiled: March 13, 2017Date of Patent: July 2, 2019Assignee: Board of Regents, The University of Texas SystemInventors: S. V. Sreenivasan, Brent Snyder, Miaomiao Yang, Shrawan Singhal, Ovadia Abed
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Publication number: 20190139456Abstract: A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently.Type: ApplicationFiled: March 21, 2017Publication date: May 9, 2019Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Aseem Sayal, Benjamin Eynon
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Patent number: 10026609Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.Type: GrantFiled: October 23, 2015Date of Patent: July 17, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Anshuman Cherala, Meghali Chopra, Roger Bonnecaze, Ovadia Abed, Bailey Yin, Akhila Mallavarapu, Shrawan Singhal, Brian Gawlik
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Patent number: 9972699Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: GrantFiled: February 26, 2018Date of Patent: May 15, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Patent number: 9972698Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: GrantFiled: February 26, 2018Date of Patent: May 15, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Patent number: 9941389Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: GrantFiled: April 19, 2016Date of Patent: April 10, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Publication number: 20170259560Abstract: Systems and methods for precision inkjet printing are disclosed. A method determining an actuation parameter associated with a pressure waveform. Based on the pressure waveform, the method also includes actuating a print head to eject a droplet from a nozzle and acquiring an image of the droplet. The method further includes processing the acquired image to estimate a volume of the droplet and based on the estimated volume of the droplet and a target volume, adjusting the acquisition parameter.Type: ApplicationFiled: March 13, 2017Publication date: September 14, 2017Inventors: S.V. Sreenivasan, Brent Snyder, Miaomiao Yang, Shrawan Singhal, Ovadia Abed
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Patent number: 9718096Abstract: An inkjet-based process for programmable deposition of thin films of a user-defined profile. Drops of a pre-cursor liquid organic material are dispensed at various locations on a substrate by a multi-jet. A superstrate is held in a roll-to-roll configuration such that a first contact of the drops is made by a front side of the superstrate thereby initiating a liquid front that spreads outward merging with the drops to form a contiguous film captured between the substrate and the superstrate. A non-equilibrium transient state of the superstrate, the contiguous film and the substrate then occurs after a duration of time. The contiguous film is then cured to crosslink it into a polymer. The superstrate is then separated from the polymer thereby leaving a polymer film on the substrate. In such a manner, non-uniform films can be formed without significant material wastage in an inexpensive manner.Type: GrantFiled: July 12, 2016Date of Patent: August 1, 2017Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn