Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polymide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polymide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield.

Abstract: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site.

Abstract: A structure (40) for holding an integrated circuit die (38) during packaging includes a support substrate (42), a release film (44) attached to the substrate (42), and a swelling agent (60). A method (34) of packaging the die (38) includes placing the die (38) on the substrate (42) with its active surface (52) and bond pads (54) in contact with the film (44). The agent (60) is applied over an adhesive coating (50) of the film (44). The agent (60) causes the adhesive (50) to swell into contact with the bond pads (54) and/or to form fillets (64) of adhesive (50) about the die (38). The die (38) is encapsulated in a molding material (72) and released from the substrate (42) as a panel (74) of dies (38). Swelling of the adhesive (50) about the bond pads (54) prevents the molding material (72) from bleeding onto the bond pads (54).

Abstract: A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. An encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.

Abstract: A structure (40) for holding an integrated circuit die (38) during packaging includes a support substrate (42), a release film (44) attached to the substrate (42), and a swelling agent (60). A method (34) of packaging the die (38) includes placing the die (38) on the substrate (42) with its active surface (52) and bond pads (54) in contact with the film (44). The agent (60) is applied over an adhesive coating (50) of the film (44). The agent (60) causes the adhesive (50) to swell into contact with the bond pads (54) and/or to form fillets (64) of adhesive (50) about the die (38). The die (38) is encapsulated in a molding material (72) and released from the substrate (42) as a panel (74) of dies (38). Swelling of the adhesive (50) about the bond pads (54) prevents the molding material (72) from bleeding onto the bond pads (54).

Abstract: Methods and apparatus are provided for encapsulating electronic devices, comprising: providing one or more electronic devices (62) with primary faces (63) having electrical contacts (69), opposed rear faces (65) and edges (64) therebetween. A sacrificial layer (70) is provided on the primary faces (63). The devices (62) are mounted on a temporary support (80) so that the sacrificial layer (70) faces toward the temporary support (80). A plastic encapsulation (86)is formed in contact with at least the lateral edges (64) of the electronic devices (62). The plastic encapsulation (86) is at least partially cured and the devices (62) and plastic encapsulation (86) separated from the temporary support (80), thereby exposing the sacrificial layer (70). The sacrificial layer (70) is removed. The devices (62) and edge-contacting encapsulation are mounted on a carrier (90) with the primary faces (63) and electrical contacts (69) exposed and, optionally, further cured.

Abstract: A method for forming a microelectronic assembly is provided. A carrier substrate (30) is provided. A sacrificial layer (38) is formed over the carrier substrate. A polymeric layer (40), including a polymeric tape (42) and a polymeric layer adhesive (44), is formed over the sacrificial layer. The polymeric layer adhesive is between the sacrificial layer and the polymeric tape. A microelectronic die (52), having an integrated circuit formed therein, is placed on the polymeric layer. The microelectronic die is encapsulated with an encapsulation material (54) to form an encapsulated structure (58). The polymeric layer and the encapsulated structure are separated from the carrier substrate. The separating of the polymeric layer and the encapsulated structure includes at least partially deteriorating the sacrificial layer.

Abstract: The invention provides an integrated device with corrosion-resistant capped copper bond pads. The capped copper bond pads include at least one copper bond pad on a semiconductor substrate. An activation layer comprising one of immersion palladium, electroless cobalt, or immersion ruthernium is disposed on the copper bond pad. A first intermediate layer of electroless nickel-boron alloy is disposed on the activation layer. A second intermediate layer comprising one of electroless nickel or electroless palladium is disposed on the first intermediate layer, and an immersion gold layer is disposed on the second intermediate layer. A capped copper bond pad and a method of forming the capped copper bond pads are also disclosed.

Abstract: A process for encapsulating an integrated circuit die (403) using a porous carrier (101). In one example, an adhesive structure (e.g. tape) is applied to a porous carrier. Integrated circuit die is then placed on the adhesive structure. The integrated circuit die is then encapsulated to form an encapsulated structure (505). The carrier is then subjected to a solvent that passes through the carrier to reduce the adhesive strength of the adhesive structure for removal of the carrier from the encapsulated structure.