Patents by Inventor Owen W. Jungroth
Owen W. Jungroth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768603Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.Type: GrantFiled: May 5, 2022Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
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Patent number: 11587874Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.Type: GrantFiled: February 24, 2020Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Sung-Taeg Kang, Pranav Kalavade, Owen W. Jungroth, Prasanna Srinivasan
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Publication number: 20220261151Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: ApplicationFiled: May 5, 2022Publication date: August 18, 2022Applicant: Micron Technology, Inc.Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
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Patent number: 11354040Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: GrantFiled: July 10, 2020Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
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Publication number: 20210265278Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Inventors: Sung-Taeg Kang, Pranav Kalavade, Owen W. Jungroth, Prasanna Srinivasan
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Patent number: 10923450Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.Type: GrantFiled: June 11, 2019Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Richard Fastow, Khaled Hasnat, Prashant Majhi, Owen W. Jungroth, Krishna Parat
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Publication number: 20200395328Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Applicant: Intel CorporationInventors: Richard Fastow, Khaled Hasnat, Prashant Majhi, Owen W. Jungroth, Krishna Parat
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Publication number: 20200341635Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Applicant: Micron Technology, Inc.Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
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Patent number: 10719237Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: GrantFiled: January 11, 2016Date of Patent: July 21, 2020Assignee: Micron Technology, Inc.Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
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Patent number: 10515973Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.Type: GrantFiled: November 30, 2017Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Deepak Thimmegowda, Owen W. Jungroth, David S. Meyaard, Khaled Hasnat
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Publication number: 20190043874Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.Type: ApplicationFiled: November 30, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: Deepak Thimmegowda, Owen W. Jungroth, David S. Meyaard, Khaled Hasnat
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Publication number: 20170199666Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.Type: ApplicationFiled: January 11, 2016Publication date: July 13, 2017Applicant: Micron Technology, Inc.Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
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Patent number: 6831862Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.Type: GrantFiled: December 26, 2002Date of Patent: December 14, 2004Assignee: Intel CorporationInventors: Kerry D. Tedrow, Balaji Srinivasan, Owen W. Jungroth
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Publication number: 20030090949Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.Type: ApplicationFiled: December 26, 2002Publication date: May 15, 2003Inventors: Kerry D. Tedrow, Balaji Srinivasan, Owen W. Jungroth
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Patent number: 6515906Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.Type: GrantFiled: December 28, 2000Date of Patent: February 4, 2003Assignee: Intel CorporationInventors: Kerry D. Tedrow, Balaji Srinivasan, Owen W. Jungroth
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Patent number: 6449211Abstract: A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.Type: GrantFiled: August 31, 2001Date of Patent: September 10, 2002Assignee: Intel CorporationInventors: Owen W. Jungroth, Rajesh Sundaram, Mase J. Taub, Rupinder K. Bains, Raymond Zeng, Binh N. Ngo, Bharat Pathak
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Patent number: 6418506Abstract: An integrated circuit (IC) memory device having an interface coupled with a volatile random access memory (RAM) array and a nonvolatile flash memory array. Data to be written from an external device to the IC memory device is initially written to the volatile RAM array to provide for fast execution of a write operation, and is then written from the volatile RAM array to the nonvolatile flash memory array via the interface in a manner that is relatively transparent to external devices and the user. The interface may be configured to transfer data from the volatile RAM array to the external device if a read request matches an address tag field stored in the volatile RAM array. Data from first and second block addresses in the volatile RAM array and flash memory array may be merged in a flash merge buffer, and validity bits may be used to ensure that potentially stale data in the flash memory array is not used and that data coherency is maintained.Type: GrantFiled: December 31, 1996Date of Patent: July 9, 2002Assignee: Intel CorporationInventors: Richard D. Pashley, Mark D. Winston, Owen W. Jungroth, David J. Kaplan
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Publication number: 20020085423Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.Type: ApplicationFiled: December 28, 2000Publication date: July 4, 2002Inventors: Kerry D. Tedrow, Balaji Srinivasan, Owen W. Jungroth
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Patent number: 6297974Abstract: A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors.Type: GrantFiled: September 27, 1999Date of Patent: October 2, 2001Assignee: Intel CorporationInventors: Ramkarthik Ganesan, Owen W. Jungroth
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Patent number: RE41217Abstract: A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors.Type: GrantFiled: October 2, 2003Date of Patent: April 13, 2010Assignee: Intel CorporationInventors: Ramkarthik Ganesan, Owen W. Jungroth