Abstract: A nonvolatile memory includes a global line. A plurality of memory blocks and a redundant block are also included in the memory, each block having a plurality of local lines and a decoder for selectively connecting the global line to one of the local lines when the decoder is enabled and for isolating the local lines from the global line when the decoder is disabled. When one of the plurality of blocks is found to be a defective block, the defective block is replaced by the redundant block. Circuitry is provided for disabling the decoder of the defective block and enabling the decoder of the redundant block whenever the defective block is addressed.

Abstract: Override control circuitry and a method for terminating a sequence for erasing or programming a computer memory are described. A command register is provided for storing a command sent by an external processor to the memory. A decoder circuit decodes the command and outputs an erase or program set-up signal if the command indicates the initiation of an erase or program sequence. A latch is coupled to the decode circuit for storing the erase or program set-up signal. An override timer is located between the latch and the memory. The override timer includes a counter which is initialized and begins counting when the erase or program set-up signal is latched. The override timer also includes a circuit that detects when the counter has reached a first count for an erase sequence and a second count for a program sequence. The circuit then generates an erase or program override signal. An erase switch detects the erase override signal and prevents the application of an erase voltage to the memory.

Abstract: A circuit for switching the source regions of reference devices used in a flash EPROM from ground potential to a potential of 3.5 volts during programming. This prevents charging of the floating gates of the reference devices on the selected word line and the discharging of the floating gates of the reference devices on the non-selected word lines.

Abstract: A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.

Abstract: Circuitry for discharging a drain of a cell of a non-volatile semiconductor memory is described. A discharge transistor is coupled between (1) the drain of the cell and (2) ground for selectably (a) providing a discharge paths to ground for the drain of the cell when the discharge transistor is enabled and (b) not providing a discharge path to ground for the drain of the cell when the discharge transistor is not enabled. Circuitry is coupled to the discharge transistor for enabling the discharge transistor for a duration that both begins and ends (1) after a first operation is performed with respect to the cell and (2) before a verify operation is performed with respect to the cell.

Abstract: A blocking architecture for use in non-volatile semiconductor memories is disclosed. This architecture minimizes device area taken up by signal lines while maximizing device yield. Additionally, this architecture minimizes the Y decoding mechanism while maximizing device performance.

Abstract: A circuit is disclosed for preventing the erasing and programming of a nonvolatile memory device during power up and power down transitions. A power supply generator incorporating an n-channel device and a w-channel device in a wired-or configuration is coupled to a programming voltage Vpp and to a circuit voltage Vcc, and generates a node voltage Vpwr which is the greater of Vpp-Vtn and Vcc-Vtw. Vtn is the gate threshold voltage of the n-channel device, while Vtw is the gate threshold voltage of the w-channel device. The node voltage Vpwr is coupled to a reference voltage generator which provides a reference voltage, a protecting voltage, and a biasing voltage for a Vcc comparator and a Vpp comparator. The Vcc comparator and the Vpp comparator compare Vref with the output of a Vcc divide-by-two circuit and a Vpp divide-by-five cirucit, respectively.

Abstract: A circuit is described for providing internal voltage margining for a flash EPROM to verify erasing and programming. Matched transistors are used to develop the internal margined voltage so as to provide a potential which is substantially independent of process variations. Different potentials are used to verify programming and erasing.

Abstract: A circuit for providing a programming potential to an electrically programmable read-only memory (EPROM) cell is disclosed. The circuit includes a matched pair of transistors coupled in series and having their gates coupled to a resistor for providing a reference potential. A decoder and latch transfers this potential to another pair of match transistors coupled in series with the EPROM cell. The reference potential is optimized for programming of the cell. The circuit is configured to substantially reduce the load line variations resulting from changes in process and temperature.