Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Abstract: Methods, systems, and computer-readable media are described herein for using a modified Kalman filter to generate attitude error corrections. Attitude measurements are received from primary and secondary attitude sensors of a satellite or other spacecraft. Attitude error correction values for the attitude measurements from the primary attitude sensors are calculated based on the attitude measurements from the secondary attitude sensors using expanded equations derived for a subset of a plurality of block sub-matrices partitioned from the matrices of a Kalman filter, with the remaining of the plurality of block sub-matrices being pre-calculated and programmed into a flight computer of the spacecraft. The propagation of covariance is accomplished via a single step execution of the method irrespective of the secondary attitude sensor measurement period.

Abstract: A method of providing data associated with reception of media content is presented. In the method, a communication device receives media content from a media content receiver via a communication network. The received media content is output to a user of the communication device. Data is then generated in the communication device which includes information identifying a channel selected by the user over which the media content receiver receives the media content. The data further includes information identifying a time period during which the communication device receives the media content. The data is transferred via the communication network to a communication node.

Abstract: An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit.

Abstract: An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit.

Abstract: Methods, systems, and computer-readable media are described herein for using a modified Kalman filter to generate attitude error corrections. Attitude measurements are received from primary and secondary attitude sensors of a satellite or other spacecraft. Attitude error correction values for the attitude measurements from the primary attitude sensors are calculated based on the attitude measurements from the secondary attitude sensors using expanded equations derived for a subset of a plurality of block sub-matrices partitioned from the matrices of a Kalman filter, with the remaining of the plurality of block sub-matrices being pre-calculated and programmed into a flight computer of the spacecraft. The propagation of covariance is accomplished via a single step execution of the method irrespective of the secondary attitude sensor measurement period.

Abstract: A method of providing data associated with reception of media content is presented. In the method, a communication device receives media content from a media content receiver via a communication network. The received media content is output to a user of the communication device. Data is then generated in the communication device which includes information identifying a channel selected by the user over which the media content receiver receives the media content. The data further includes information identifying a time period during which the communication device receives the media content. The data is transferred via the communication network to a communication node.

Abstract: A method of providing data associated with reception of media content is presented. In the method, a communication device receives media content from a media content receiver via a communication network. The received media content is output to a user of the communication device. Data is then generated in the communication device which includes information identifying a channel selected by the user over which the media content receiver receives the media content. The data further includes information identifying a time period during which the communication device receives the media content. The data is transferred via the communication network to a communication node.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.

Abstract: A method of providing data associated with reception of media content is presented. In the method, a communication device receives media content from a media content receiver via a communication network. The received media content is output to a user of the communication device. Data is then generated in the communication device which includes information identifying a channel selected by the user over which the media content receiver receives the media content. The data further includes information identifying a time period during which the communication device receives the media content. The data is transferred via the communication network to a communication node.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.

Abstract: Techniques for sharing content information between members of a virtual user group without compromising the privacy of the members. A user can identify content information to be shared with other members of a virtual user group using a user computer system. The content information is then communicated to the other members of the virtual user group and can be accessed by members of the virtual user group in such a manner that the privacy of the user and of the other members of the virtual user group is not compromised. The present invention preserves user privacy by controlling and minimizing the amount of user-related information available/accessible to server systems hosting the virtual user groups.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively.

Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Abstract: Techniques for sharing content information between members of a virtual user group without compromising the privacy of the members. A user can identify content information to be shared with other members of a virtual user group using a user computer system. The content information is then communicated to the other members of the virtual user group and can be accessed by members of the virtual user group in such a manner that the privacy of the user and of the other members of the virtual user group is not compromised. The present invention preserves user privacy by controlling and minimizing the amount of user-related information available/accessible to server systems hosting the virtual user groups.