Patents by Inventor P. Nayak
P. Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7138714Abstract: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.Type: GrantFiled: February 11, 2005Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Du B. Nguyen, Birendra N. Agarwala, Conrad A Barile, Jawahar P. Nayak, Hazara S. Rathore
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Publication number: 20060230035Abstract: An information retrieval system includes a query revision architecture that integrates multiple different query revisers, each implementing one or more query revision strategies. A revision server receives a user's query, and interfaces with the various query revisers, each of which generates one or more potential revised queries. The revision server evaluates the potential revised queries, and selects one or more of them to provide to the user. A session-based reviser suggests one or more revised queries, given a first query, by calculating an expected utility for the revised query. The expected utility is calculated as the product of a frequency of occurrence of the query pair and an increase in quality of the revised query over the first query.Type: ApplicationFiled: March 30, 2005Publication date: October 12, 2006Inventors: David Bailey, Alexis Battle, Benedict Gomes, P. Nayak
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Publication number: 20060230022Abstract: An information retrieval system includes a query revision architecture that integrates multiple different query revisers, each implementing one or more query revision strategies. A revision server receives a user's query, and interfaces with the various query revisers, each of which generates one or more potential revised queries. The revision server evaluates the potential revised queries, and selects one or more of them to provide to the user.Type: ApplicationFiled: March 29, 2005Publication date: October 12, 2006Inventors: David Bailey, Alexis Battle, Benedict Gomes, P. Nayak
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Publication number: 20060230005Abstract: An information retrieval system includes a query revision architecture that integrates multiple different query revisers, each implementing one or more query revision strategies. A revision server receives a user's query, and interfaces with the various query revisers, each of which generates one or more potential revised queries. The revision server evaluates the potential revised queries, and selects one or more of them to provide to the user. A confidence estimator and method provide the ability to improve the likelihood of success of suggested revised queries derived from various revision strategies. This is accomplished by tracking user queries, query revision links, results associated with revised queries, and various features of the original query and revised queries. This data is then analyzed using a predictive model to generate a set of rules that can be used to estimate the likelihood of a revised query being a successful revision for a given query.Type: ApplicationFiled: March 30, 2005Publication date: October 12, 2006Inventors: David Bailey, Alexis Battle, Benedict Gomes, P. Nayak
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Publication number: 20060224554Abstract: An information retrieval system includes a query revision architecture providing one or more query revisers, each of which implements a query revision strategy. A query rank reviser suggests known highly-ranked queries as revisions to a first query by initially assigning a rank to all queries, and identifying a set of known highly-ranked queries (KHRQ). Queries with a strong probability of being revised to a KHRQ are identified as nearby queries (NQ). Alternative queries that are KHRQs are provided as candidate revisions for a given query. For alternative queries that are NQs, the corresponding known highly-ranked queries are provided as candidate revisions.Type: ApplicationFiled: November 22, 2005Publication date: October 5, 2006Inventors: David Bailey, Alexis Battle, David Cohn, Barbara Engelhardt, P. Nayak
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Patent number: 7067902Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.Type: GrantFiled: December 2, 2003Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Habib Hichri, Xiao H. Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw
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Patent number: 6978966Abstract: A system and method for performing in-orbit alignment calibration using on-board attitude sensors to improve reflector alignment after deployment to improve spacecraft pointing.Type: GrantFiled: February 2, 2004Date of Patent: December 27, 2005Assignee: The Boeing CompanyInventors: Hanching Grant Wang, Richard A. Fowell, Arunkumar P. Nayak
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Patent number: 6972209Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: GrantFiled: November 27, 2002Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Patent number: 6750109Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.Type: GrantFiled: July 1, 2002Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: James A. Culp, Jawahar P. Nayak, Werner A. Rausch, Melanie J. Sherony, Steven H. Voldman, Noah D. Zamdmer
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Publication number: 20040101663Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engel, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Patent number: 6701362Abstract: A method for creating personalized user profiles using a client computer. A client computer executes a method which monitors user activities and collects content and context information based on the monitored user activities. The client computer processes the content and context information to determine concepts of interest to the user and the user's level of interest in the concepts. Information related to the concepts and the user's interest level associated with the concepts is used to create a personalized profile for the user on the client computer.Type: GrantFiled: February 23, 2000Date of Patent: March 2, 2004Assignee: PurpleYogi.com Inc.Inventors: Ramesh Subramonian, Ramana Venkata, Pangal P. Nayak, Joy A. Thomas
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Patent number: 6581072Abstract: Techniques for identifying and accessing documents (e.g., web pages) of interest to a user in a network environment without compromising the user's privacy. A user system receives index information comprising information related to documents stored in a network environment. The index information is then used to identify and access documents of interest to the user. The identification of documents of interest to the user is performed on the user system thus obviating the need to provide any information to search engines executing on remote servers. The present invention preserves user privacy by controlling and minimizing the communication and collection of user-related information from the user system. Merely by way of example, the present invention allows users to identify and access web pages from web servers coupled to a communication network such as the Internet without compromising user privacy.Type: GrantFiled: May 17, 2001Date of Patent: June 17, 2003Inventors: Rakesh Mathur, Ramesh Subramonian, Ramana Venkata, Pangal P. Nayak, Joy A. Thomas
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Patent number: 6475555Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.Type: GrantFiled: October 29, 1999Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Jon A. Casey, Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Brenda L. Peterson, Robert A. Rita
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Publication number: 20020149058Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.Type: ApplicationFiled: July 1, 2002Publication date: October 17, 2002Applicant: International Business Machines CorporationInventors: James A. Culp, Jawahar P. Nayak, Werner A. Rausch, Melanie J. Sherony, Steven H. Voldman, Noah D. Zamdmer
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Patent number: 6429482Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.Type: GrantFiled: June 8, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: James A. Culp, Jawahar P. Nayak, Werner A. Rausch, Melanie J. Sherony, Steven H. Voldman, Noah D. Zamdmer
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Publication number: 20020023779Abstract: A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.Type: ApplicationFiled: October 18, 2001Publication date: February 28, 2002Inventors: Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Keith C. O'Neil, Brenda L. Peterson
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Patent number: 6341417Abstract: A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.Type: GrantFiled: September 23, 1999Date of Patent: January 29, 2002Assignee: International Business Machines CorporationInventors: Dinesh Gupta, Lester Wynn Herron, John U. Knickerbocker, David C. Long, Jawahar P. Nayak, Keith C. O'Neil, Brenda L. Peterson
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Publication number: 20020009539Abstract: A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.Type: ApplicationFiled: October 29, 1999Publication date: January 24, 2002Inventors: JON A. CASEY, DINESH GUPTA, LESTER WYNN HERRON, JOHN U. KNICKERBOCKER, DAVID C. LONG, JAWAHAR P. NAYAK, BRENDA L. PETERSON, ROBERT A. RITA
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Patent number: 6289268Abstract: A star tracker coupled to the spacecraft having a star catalog associated therewith. A sun sensor is coupled to the spacecraft. A control processor is coupled to the star tracker and the sun sensor. The processor obtains star data using a star tracker and an on-board star catalog. The processor generates a coarse attitude of the spacecraft as a function of the star data, and establishes a track on at least one star in the on-board star catalog. The processor calculates a sun tracking rate, and obtains a normal phase attitude as a function of the star data and the coarse attitude. The information is used to slew the spacecraft to a desired attitude.Type: GrantFiled: March 2, 2000Date of Patent: September 11, 2001Assignee: Hughes Electronics Corp.Inventors: Garry Didinsky, Arunkumar P. Nayak, Rongsheng Li, Yeong-Wei A. Wu, Jeffrey A. Kurland, David D. Needelman
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Publication number: 20010006116Abstract: A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.Type: ApplicationFiled: January 18, 2001Publication date: July 5, 2001Applicant: International Business Machines CorporationInventors: James M. Blazick, Michael E. Cropp, James N. Humenik, Gerald H. Leino, Jawahar P. Nayak, Frank V. Ranalli, Deborah A. Sylvester, John A. Trumpetto, James C. Utter, Rao V. Vallabhaneni, Renne L. Weisman