Patents by Inventor Péter Ónody
Péter Ónody has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220200580Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.Type: ApplicationFiled: February 17, 2022Publication date: June 23, 2022Inventors: Péter Onódy, András V. Horváth
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Publication number: 20220187861Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Inventors: Viktor Zsolczai, András V. Horváth, Péter Onódy
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Publication number: 20220187862Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.Type: ApplicationFiled: December 16, 2020Publication date: June 16, 2022Inventors: Péter Onódy, Tamás Marozsák, Viktor Zsolczai, András V. Horváth
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Publication number: 20220115941Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventors: Michael R. May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamás Marozsák, András V. Horváth
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Patent number: 11258432Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.Type: GrantFiled: December 17, 2020Date of Patent: February 22, 2022Assignee: Skyworks Solutions, Inc.Inventors: Péter Onódy, András V. Horváth
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Patent number: 11057029Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.Type: GrantFiled: November 25, 2019Date of Patent: July 6, 2021Assignee: Silicon Laboratories Inc.Inventors: Alan L. Westwick, Peter Onody, András V. Horváth, Tamás Marozsák
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Publication number: 20210159898Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Alan L. Westwick, Peter Onody, András V. Horváth, Tamás Marozsák
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Patent number: 10942217Abstract: A method for calibrating an isolator product includes generating a differential pair of signals on a differential pair of nodes at an input of a demodulator circuit of a receiver signal path of a first integrated circuit die of the isolator product based on a received differential pair of signals. The method includes generating a diagnostic output signal having a level corresponding to an average amplitude of the differential pair of signals. The method includes driving the diagnostic output signal to an output terminal of the isolator product. The method may include transmitting a diagnostic signal using a carrier signal having a frequency by a second integrated circuit die via an isolation channel. The method may include, during the transmitting, sweeping the frequency of the carrier signal across a frequency band. The method may include, during the sweeping, capturing the diagnostic output signal via the output terminal.Type: GrantFiled: July 31, 2019Date of Patent: March 9, 2021Assignee: Silicon Laboratories Inc.Inventors: Mohammad Al-Shyoukh, Peter Onody
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Publication number: 20210033662Abstract: A method for calibrating an isolator product includes generating a differential pair of signals on a differential pair of nodes at an input of a demodulator circuit of a receiver signal path of a first integrated circuit die of the isolator product based on a received differential pair of signals. The method includes generating a diagnostic output signal having a level corresponding to an average amplitude of the differential pair of signals. The method includes driving the diagnostic output signal to an output terminal of the isolator product. The method may include transmitting a diagnostic signal using a carrier signal having a frequency by a second integrated circuit die via an isolation channel. The method may include, during the transmitting, sweeping the frequency of the carrier signal across a frequency band. The method may include, during the sweeping, capturing the diagnostic output signal via the output terminal.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Mohammad Al-Shyoukh, Peter Onody
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Patent number: 10153909Abstract: In some embodiments, a powered device includes a powered device circuit, which may include a maintain power signature (MPS) circuit configured to compare a sense current to a reference current. In a first mode, the MPS circuit may be configured to automatically generate an MPS signal when the sense current is less than the reference current.Type: GrantFiled: July 6, 2015Date of Patent: December 11, 2018Assignee: Silicon Laboratories Inc.Inventors: Vince András Horváth, Tamás Marozsák, Péter Onódy, John Gammel
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Patent number: 9954430Abstract: In some embodiments, powered devices, circuits, and methods are disclosed that may include biasing a hot swap switch to couple a capacitor of a DC-DC converter to negative supply node when an input voltage exceeds a threshold and biasing a telephony switch to couple a positive supply node to a negative supply node when the input voltage exceeds the threshold. Further, the method may further include deactivating the hot swap switch after a period of time, and continuing to bias the telephony switch.Type: GrantFiled: July 15, 2015Date of Patent: April 24, 2018Assignee: Silicon Laboratories Inc.Inventors: Vince András Horváth, Tamás Marozsák, Péter Onódy, John Gammel
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Publication number: 20170019262Abstract: In some embodiments, powered devices, circuits, and methods are disclosed that may include biasing a hot swap switch to couple a capacitor of a DC-DC converter to negative supply node when an input voltage exceeds a threshold and biasing a telephony switch to couple a positive supply node to a negative supply node when the input voltage exceeds the threshold. Further, the method may further include deactivating the hot swap switch after a period of time, and continuing to bias the telephony switch.Type: ApplicationFiled: July 15, 2015Publication date: January 19, 2017Applicant: Silicon Laboratories Inc.Inventors: Vince András Horváth, Tamás Marozsák, Péter Onódy, John Gammel
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Publication number: 20170012787Abstract: In some embodiments, a powered device includes a powered device circuit, which may include a maintain power signature (MPS) circuit configured to compare a sense current to a reference current. In a first mode, the MPS circuit may be configured to automatically generate an MPS signal when the sense current is less than the reference current.Type: ApplicationFiled: July 6, 2015Publication date: January 12, 2017Applicant: SILICON LABORATORIES INC.Inventors: Vince András Horváth, Tamás Marozsák, Péter Onódy, John Gammel
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Patent number: 9438290Abstract: An RF receiver includes an RF signal reception path to process an input signal for the receiver for a first mode of the receiver; an oscillator; and a harmonic generator. The harmonic generator generates a harmonic signal in response to operation of the oscillator to replace the input signal with the harmonic signal for a second mode of the receiver.Type: GrantFiled: September 25, 2011Date of Patent: September 6, 2016Assignee: Silicon Laboratories Inc.Inventors: Hendricus De Ruijter, Tamas Marozsak, Peter Onody
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Patent number: 9094042Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.Type: GrantFiled: August 9, 2013Date of Patent: July 28, 2015Assignee: Silicon Laboratories Inc.Inventors: Péter Onódy, Abdulkerim L. Coban
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Publication number: 20150042498Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: Silicon Laboratories Inc.Inventors: Peter Onody, Abdulkerim L. Coban
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Patent number: 8903332Abstract: In an embodiment, a circuit device for coupling to an antenna includes a first impedance matching circuit configured to couple to the antenna and a second impedance matching circuit configured to couple to the antenna. The circuit device further includes a power amplifier coupled to the first impedance matching circuit and includes a low-noise amplifier coupled to the second impedance matching circuit. Additionally, the circuit device includes a selectable impedance adjustment circuit coupled between the low-noise amplifier and the second impedance matching circuit, which selectable impedance adjustment circuit is configured to selectively adjust an impedance associated with the low-noise amplifier when the power amplifier is transmitting a signal through the antenna.Type: GrantFiled: June 23, 2009Date of Patent: December 2, 2014Assignee: Silicon Laboratories Inc.Inventors: Péter Onódy, Attila Zolomy, Eric Unruh
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Patent number: 8643391Abstract: A method and apparatus for determining an RC (resistive-capacitive) time constant is disclosed. In one embodiment, a method comprises determining a first period of oscillation when an oscillator is operating in a first configuration. The method further comprises determining a second period of oscillation when the oscillator is operating in a second configuration. A measurement circuit is configured to determine a resistive-capacitive (RC) time constant of the oscillator by determining a mean of the first and second periods.Type: GrantFiled: September 30, 2011Date of Patent: February 4, 2014Assignee: Silicon Laboratories Inc.Inventors: William W. K. Tang, Michael J. Mills, Péter Onódy, Gerald D. Champagne
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Patent number: 8531325Abstract: A delta-sigma analog-to-digital converter (ADC) is disclosed. In one embodiment, the delta-sigma ADC includes a dual mode resonator and a plurality of switches. The delta-sigma ADC is configured to operate in a real modulation mode or a complex modulation mode based on settings of the plurality of switches.Type: GrantFiled: September 29, 2011Date of Patent: September 10, 2013Assignee: Silicon Laboratories Inc.Inventor: Péter Onódy
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Publication number: 20130083868Abstract: A delta-sigma analog-to-digital converter (ADC) is disclosed. In one embodiment, the delta-sigma ADC includes a dual mode resonator and a plurality of switches. The delta-sigma ADC is configured to operate in a real modulation mode or a complex modulation mode based on settings of the plurality of switches.Type: ApplicationFiled: September 29, 2011Publication date: April 4, 2013Inventor: Péter Onódy