Abstract: Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.

Abstract: Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.

Abstract: An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.

Abstract: An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of pMOS transistors to a second pMOS gate terminal of a second pMOS transistor of the pair of pMOS transistors, and tying at least a first pre-designated body terminal of at least one transistor selected from the group including essentially of a pair of pMOS transistors and a pair of nMOS transistors to at least a second pre-designated terminal of at least one pre-designated transistor selected from the group including essentially of the pair of pMOS transistors and the pair of nMOS transistors.

Abstract: A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9?? a through any metal segment in the parametrically modeled circuit.

Abstract: An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one example embodiment, this is achieved by applying a body bias voltage VBB to the integrated circuit to compensate for the lifetime performance drift due to hot carrier and NBTI induced aging.

Abstract: According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and CHC for transistors, those caused due to electromigration in case of interconnects). As a result, the fabricated ICs may be less susceptible to such degradations. The features are extended to model complex circuit blocks and also account for different degrees of stress that different circuit blocks are subjected to, in a same age of operation.

Abstract: An aspect of the present invention enables burn-in tests to reduce variations due to process spread in fabricated integrated circuits (IC). Fabricated ICs are classified into multiple categories based on performance characteristics (e.g., operational speed) indicative of the extent of process spread in the ICs. The ICs are subjected to burn-in tests, with the severity of stress parameters applied during a burn-in test being proportional to the performance characteristics. As a result, process spread exhibited by the ICs (post burn-in) is reduced.

Abstract: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.

Abstract: An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of pMOS transistors to a second pMOS gate terminal of a second pMOS transistor of the pair of pMOS transistors, and tying at least a first pre-designated body terminal of at least one transistor selected from the group including essentially of a pair of pMOS transistors and a pair of nMOS transistors to at least a second pre-designated terminal of at least one pre-designated transistor selected from the group including essentially of the pair of pMOS transistors and the pair of nMOS transistors.

Abstract: A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9?? a through any metal segment in the parametrically modeled circuit.

Abstract: An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance.