Patents by Inventor Pan

Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240190868
    Abstract: A compound of formula I: Each variable is defined herein. Also disclosed are a pharmaceutical composition containing a compound of formula I, a method of treating cancer using such a compound, and a method of inhibiting SOS1 with the compound.
    Type: Application
    Filed: November 9, 2023
    Publication date: June 13, 2024
    Inventors: Kuo-Long Yu, Sanjeev Kumar, Bin Liu, Weitao Pan
  • Publication number: 20240190091
    Abstract: A device includes a water storage tank, a control cabin and an operation cabin which are sequentially connected from top to bottom, the operation cabin includes a sealing zone and an operation zone, the sealing zone is located on an inner wall of the operation cabin, a pressure difference between an internal pressure and an external pressure is adjusted to make the maintenance enhancing device separated from or absorbed on a subsea pipeline, and the operation zone is located between the sealing zone and the subsea pipeline.
    Type: Application
    Filed: January 16, 2024
    Publication date: June 13, 2024
    Applicant: JIANGSU UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Yongmei ZHU, Hongzhang PAN, Jian ZHANG, Shijie SU, Suzhou ZHANG, Chuxiang LIN
  • Publication number: 20240194619
    Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
    Type: Application
    Filed: February 18, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan
  • Publication number: 20240191008
    Abstract: Provided is an amination method for a polystyrene-type resin, and a method for immobilizing an enzyme using an aminated polystyrene-type resin. The amination method includes: in a solvent, a catalyst is used to catalyze a polystyrene-type resin and an enamine salt to perform a Friedel-Crafts alkylation reaction, to obtain an aminated polystyrene-type resin, herein the catalyst is a Lewis acid catalyst. By means of the Friedel-Crafts alkylation reaction, the enamine salt is grafted onto the polystyrene-type resin, and the polystyrene-type resin is aminated. The conditions of the Friedel-Crafts alkylation reaction are easy to control, the post-treatment process is simple, and it is only necessary to remove the catalyst and the unreacted enamine salt by washing. Therefore, the above amination method in the present application has few steps and is simple and easy to implement. Meanwhile, the amination method further avoids the use of a noble metal catalyst, thereby reducing production cost.
    Type: Application
    Filed: May 10, 2021
    Publication date: June 13, 2024
    Inventors: Hao HONG, Yi XIAO, Na ZHANG, Han LIN, Long PAN, Williams VYASA, Liteng MA, Yuxia CUI, Yanyan GAO
  • Publication number: 20240193042
    Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 13, 2024
    Inventors: Jun Wang, De Hua Guo, Jia Ling Pan, Kui Ding, Kun Liu
  • Publication number: 20240194525
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventors: Yu-Jen CHANG, Hua Feng CHEN, Kuo-Hua PAN, Min-Yann HSIEH
  • Publication number: 20240192981
    Abstract: Embodiments of exitless guest to host (G2H) notification are described. In some embodiments, G2H is provided via an instruction. An exemplary processor includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and execution processing resources to execute the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a physical or virtual processor.
    Type: Application
    Filed: June 25, 2021
    Publication date: June 13, 2024
    Inventors: Wei WANG, Kun TIAN, Gilbert NEIGER, Rajesh SANKARAN, Asit MALLICK, Jr-Shian TSAI, Jacob Jun PAN, Mesut ERGIN
  • Publication number: 20240193377
    Abstract: A method, computer system, and a computer program product for training a machine learning model are provided. A machine learning model may be split into a lower portion and an upper portion. The lower portion includes at least one layer. The upper portion includes at least one layer. The lower portion may be pre-trained via a generator task and via alternating between inputting of monolingual text data and multilingual text data. The upper portion may be pre-trained via a discriminator task. The pre-trained lower portion may be joined to the pre-trained upper portion to form a trained multilingual machine learning model.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Inventors: LIN PAN, Haode Qi, Ladislav Kunc, Saloni Potdar
  • Publication number: 20240195740
    Abstract: Examples described herein relate to a network agent, when operational, to: receive a packet, determine transmit rate-related information for a sender network device based at least on operational and telemetry information accumulated in the received packet, and transmit the transmit rate-related information to the sender network device. In some examples, the network agent includes a network device coupled to a server, a server, or a network device. In some examples, the operational and telemetry information comprises: telemetry information generated by at least one network device in a path from the sender network device to the network agent.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 13, 2024
    Applicant: Intel Corporation
    Inventors: Rong Pan, Pedro Yebenes Segura, Roberto Penaranda Cebrian, Robert Southworth, Malek Musleh, Jeongkeun Lee, Changhoon Kim
  • Publication number: 20240193168
    Abstract: Various embodiments provide for a registry for augmented reality (AR) objects, which can provide AR objects to a client device to support various software or hardware applications. For instance, some embodiments provide for an AR object registry that facilitates or enables registration of one or more AR objects in association with one or more locations across a planet.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: Jennica Pounds, Qi Pan, Brent Michael Barkman, Ozi Egri
  • Publication number: 20240195772
    Abstract: Embodiments of the present application disclose an information interaction method: when a user wishes to add tags to a plurality of associated objects, the user only needs to trigger a tag adding operation for one of the objects thereamong. Thus, the number of tag adding operations which the user needs to trigger is reduced, the speed of tag adding is increased, and user operations are simplified. The embodiments of the present application provide a task-based information processing method: a first user may view, on a first page, information of at least one task related thereto, without needing to separately open pages corresponding to each tag, and thus user operation is simple. The present application discloses a schedule creation method: after a user triggers a schedule adding operation in an associated page of a first tag, the first tag is automatically brought into a schedule adding page, and a schedule comprising the first tag may be generated.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 13, 2024
    Inventors: Yuhao PAN, Liyue ZHAO
  • Publication number: 20240194688
    Abstract: An array substrate having a connection pad in a connection pad area is provided. The connection pad includes a plurality of first probe contact pads, a plurality of second probe contact pads, a plurality of first connection lines coupled to the plurality of first probe contact pads, respectively, and a plurality of second connection lines coupled to the plurality of second probe contact pads, respectively; the plurality of first connection lines and the plurality of second connection lines being in two different layers. A total number of conductive layers electrically connected to a respective first connection line of the plurality of first connection lines is different from a total number of conductive layers electrically connected to a respective second connection line of the plurality of second connection lines.
    Type: Application
    Filed: October 18, 2021
    Publication date: June 13, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Guoying Wang, Pan Xu, Dacheng Zhang, Xing Zhang, Ying Han, Chengyuan Luo, Zhen Song
  • Publication number: 20240194630
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 13, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240194758
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Inventors: Zhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG
  • Publication number: 20240194789
    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.
    Type: Application
    Filed: February 27, 2024
    Publication date: June 13, 2024
    Inventors: Jung Taek Kim, Seok Hoon Kim, Pan Kwi Park, Moon Seung Yang, Seo Jin Jeong, Min-Hee Choi, Ryong Ha
  • Publication number: 20240194547
    Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 13, 2024
    Inventors: Ling Pan, Seng Kim Ye, Hong Wan Ng, Kelvin Aik Boo Tan, See Hiong Leow
  • Publication number: 20240194356
    Abstract: A medical document analysis method includes following steps: performing recursive search based on keywords extracted from first medical documents to obtain second medical documents; analyzing feature labels of the second medical documents; projecting the second medical documents onto a multi-dimensional map according to the feature labels; estimating second symptoms from a first symptom; selecting third medical documents based on the first symptom and the second symptom from the multi-dimensional map; analyzing correlation between the third medical documents and their respective feature labels in the multi-dimensional map to form a label topology map; and selecting a target branch path from branch paths in the label topology map, and displaying information about the target branch path.
    Type: Application
    Filed: May 18, 2023
    Publication date: June 13, 2024
    Applicant: ASG Inspiration Laboratory Ltd.
    Inventors: Johnson LEE, Jao Juen HUNG, Sung Tsai YU, Shih Pan CHAO, Hao-Wei HUANG
  • Patent number: 12005076
    Abstract: A soluble zinc polyphosphate complex made by combining ingredients which include an inorganic zinc salt and a plurality of long chain polyphosphates having 6 or more phosphate polymer units, the relative amount of inorganic zinc salt and long chain polyphosphates providing a phosphorus to zinc mole ratio of at least 6:1. Further provided is a method of making this soluble zinc polyphosphate.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: June 11, 2024
    Assignee: Colgate-Palmolive Company
    Inventors: Baohua Qiao, Long Pan, Gregory Szewczyk, Ravi Subramanyam
  • Patent number: 12009742
    Abstract: An electric power conversion system comprising: an alternating current (AC) source comprising a plurality of AC terminals for conducting AC power; a voltage source electrically coupled to the AC terminals; and a controller operably coupled to the voltage source, the controller being configured to: operate the voltage source to apply a fault reducing voltage at the AC terminals that reduces an AC line-to-line fault current (If).
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: June 11, 2024
    Assignees: General Electric Company, General Electric Deutschland Holding GmbH
    Inventors: Hridya Ittamveettil, Kum Kang Huh, Vandana Prabhakar Rallabandi, Di Pan, Rajib Datta, Mohamed Osama
  • Patent number: D1031124
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 11, 2024
    Assignee: SHENZHEN SNC OPTO ELECTRONIC CO., LTD
    Inventors: Nianhua Pan, Peng Huang, Anle Zhao