Patents by Inventor Pankaj Sharma

Pankaj Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12234203
    Abstract: The present invention relates to process for the preparation of cannabidiol (A) from the coupling of (D) and (E) through the intermediates (C) and (D) starting from compound (B). The invention further relates to the novel compounds (B), (C), (D) and (E) and reagents used in this process. More specifically, this invention provides the manufacturing of Cannabidiol (A) in milligram to gram or kilogram scale.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: February 25, 2025
    Assignee: COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH AN INDIAN REGISTERED BODY INCORPORATED UNDER THE REGN. OF SOC. ACT (ACT XXI OF 1860)
    Inventors: Radhika Anand, Sumit Sharma, Pankaj Singh Cham, Veeranjaneyulu Gannedi, Mukesh Kumar, Varun Pratap Singh, Vishav Prakash Rahul, Ram Asrey Vishwakarma, Parvinder Pal Singh
  • Publication number: 20250031951
    Abstract: Provided herein is a method of determining an adjustment for the lens of a camera comprising: determining if liquid lens hardware is present; in accordance with determining that liquid lens hardware is present, commanding an initial voltage for the liquid lens hardware; setting a high threshold focus metric; the camera capturing an image frame and converting the image frame to data; calculating a focus metric of the image frame data and comparing the image frame data focus metric to the high threshold focus metric; and in accordance with the image frame data focus metric being higher than the high threshold focus metric, commanding a change in voltage to be delivered to the liquid lens hardware.
    Type: Application
    Filed: October 11, 2024
    Publication date: January 30, 2025
    Applicant: Stryker Corporation
    Inventors: Levey Trac TRAN, Chien Mien PANG, Ajay RAMESH, Rohit SUBRAMANIAN, Pankaj SHARMA
  • Publication number: 20250022300
    Abstract: Vehicle systems and methods are provided for monitoring symbology in a video stream associated with a software application. A method involves a programmable device identifying, within a first portion of a frame of a video stream, metadata identifying one or more characteristics of a symbol to be analyzed and corresponding indicia of an expected location of the symbol within a second portion of the frame, extracting a subset of pixels from the second portion of the frame encompassing the expected location, and providing the extracted subset of pixels from the second portion of the frame and the metadata from the first portion of the frame to a hardware symbol detector configurable to determine one or more metrics associated with the symbol based on the extracted subset of pixels and the metadata and provide the one or more metrics to the software application.
    Type: Application
    Filed: October 18, 2023
    Publication date: January 16, 2025
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Scott Nagy, Edward Colin Layden, Pankaj Sharma
  • Publication number: 20250024675
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.
    Type: Application
    Filed: October 2, 2024
    Publication date: January 16, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, Naveen Kaushik, Pankaj Sharma
  • Patent number: 12190147
    Abstract: The disclosure herein describes platform-level checkpointing for deep learning (DL) jobs. The checkpointing is performed through capturing two kinds of state data: (i) GPU state (device state), and (ii) CPU state (host state). The GPU state includes GPU data (e.g., model parameters, optimizer state, etc.) that is located in the GPU and GPU context (e.g., the default stream in GPU, various handles created by the libraries such as DNN, Blas, etc.). Only a fraction of the GPU memory is copied because the checkpointing is done in a domain-aware manner. The “active” memory contains useful data like model parameters. To be able to capture the useful data, memory management is controlled to identify which parts of the memory are active. Also, to restore the destination GPU to the same context/state, a mechanism is used to capture such state-changing events on an original GPU and replayed on a destination GPU.
    Type: Grant
    Filed: June 26, 2021
    Date of Patent: January 7, 2025
    Assignee: Microsoft Technology Licensing, LLC.
    Inventors: Muthian Sivathanu, Srinidhi Viswanatha, Dharma Kiritkumar Shukla, Nipun Kwatra, Ramachandran Ramjee, Rimma Vladimirovna Nehme, Pankaj Sharma, Bhalakumaaran Erode Ranganathan, Vaibhav Sharma
  • Patent number: 12154853
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: November 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Naveen Kaushik, Sidhartha Gupta, Pankaj Sharma, Haitao Liu
  • Publication number: 20240385713
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Pankaj Sharma
  • Patent number: 12144489
    Abstract: A surgical camera system comprising: a camera head including a housing; an image sensor within the housing; and the housing including a liquid lens therein for focusing an image received in the housing prior to transmission of the image to the image sensor, and a fixed solid lens adjacent the liquid lens.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 19, 2024
    Assignee: Stryker Corporation
    Inventors: Levey Trac Tran, Chien Mien Pang, Ajay Ramesh, Rohit Subramanian, Pankaj Sharma
  • Patent number: 12137553
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: November 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, Naveen Kaushik, Pankaj Sharma
  • Publication number: 20240357112
    Abstract: Methods, systems, and bitstream syntax are described for the fusion of latent features in multi-level, end-to-end, neural networks used in image and video compression. The fused architecture may be static or dynamic based on image characteristics (e.g., natural images versus screen content images) or other coding parameters, such as bitrate constrains or rate-distortion optimization. A variety of multi-level fusion architectures are discussed.
    Type: Application
    Filed: August 3, 2022
    Publication date: October 24, 2024
    Applicant: Dolby Laboratories Licensing Corporation
    Inventors: Arunkumar MOHANANCHETTIAR, Jay Nitin SHINGALA, Pankaj SHARMA, Nijil KOLLERI, Peng YIN, Arjun ARORA, Fangjun PU, Taoran LU, Sean Thomas MCCARTHY, Walter J. HUSAK
  • Patent number: 12119176
    Abstract: Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 15, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Pankaj Sharma, Sidhartha Gupta
  • Patent number: 12079415
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: September 3, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Pankaj Sharma
  • Publication number: 20240268091
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first conductive region; a second conductive region; a memory cell between the first and second conductive regions and including a first transistor including a first region coupled to the first and second conductive regions, and a charge storage structure separated from the first conduction region, and a second transistor including a second region coupled to the charge storage structure and the second conductive region; and a structure separated from the first region, the charge storage structure, and the second region by a dielectric structure, the structure forming part of a gate of the first transistor and the second transistor, and the structure including a first portion adjacent the dielectric structure, and a second portion adjacent the first portion, wherein the first portion includes a semiconductor material and the second portion includes a conductive material.
    Type: Application
    Filed: February 5, 2024
    Publication date: August 8, 2024
    Inventors: Kamal M. Karda, Pankaj Sharma, Manuj Nahar, Nicholas R. Tapias, Scott E. Sills
  • Patent number: 11970971
    Abstract: A turbofan engine is provided. The turbofan engine includes a fan; a turbomachine operably coupled to the fan for driving the fan, wherein the turbomachine, the fan, or both include an engine component; a heat source; and a heat transfer system configured to reduce ice buildup or ice formation in the engine component, the heat transfer system in communication with the heat source, the heat transfer system comprising: a first heat transfer component in communication with the heat source; and a second heat transfer component that extends from the first heat transfer component to or through the engine component, wherein the first heat transfer component comprises one of a heat pipe or a graphene rod, and wherein the second heat transfer component comprises the other of the heat pipe or the graphene rod.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 30, 2024
    Assignees: General Electric Company, General Electric Deutschland Holding GmbH
    Inventors: Rajani Bhanu Poornima M, Vilas Kawaduji Bokade, Subramani Adhiachari, Sesha Subramanian, Pankaj Sharma, Ashish Sharma, Scott Alan Schimmels
  • Patent number: 11960549
    Abstract: Data is collected from a network graph, wherein the collected data is useful for training a machine learning model on a query domain. A domain-specific template corresponding to the query domain is received, the domain-specific template defining one or more classifiers to guide collection of content relevant to the query domain from the network graph. A collection starting point is analyzed based on the one or more classifiers of the domain-specific template to identify one or more relevant instances of the content. The one or more identified relevant instances of the content are added to a contextual protocol package. Each identified relevant instance of the content is analyzed based on the one or more classifiers of the domain-specific template to identify one or more additional relevant instances of the content. The one or more identified additional relevant instances of the content are added to the contextual protocol package.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 16, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yu Zhang, Pankaj Sharma, Manish Shukla, Grigoriy A Orlov
  • Publication number: 20240074138
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line; a second data line adjacent the first data line and separated from the first data line by a first dielectric structure; and a memory cell formed over the first and second data lines. The memory cell includes a first transistor including a first channel region formed over and coupled to the first data line, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over and coupled to the second data line, wherein the charge storage structure is formed over and coupled to the second channel region; and a second dielectric structure between the first channel region and each of the second channel region and the charge storage structure.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 29, 2024
    Inventors: Durai Vishak Nirmal Ramaswamy, Karthik Sarpatwari, Kamal M. Karda, Pankaj Sharma
  • Publication number: 20230349324
    Abstract: A turbofan engine is provided. The turbofan engine includes a fan; a turbomachine operably coupled to the fan for driving the fan, wherein the turbomachine, the fan, or both include an engine component; a heat source; and a heat transfer system configured to reduce ice buildup or ice formation in the engine component, the heat transfer system in communication with the heat source, the heat transfer system comprising: a first heat transfer component in communication with the heat source; and a second heat transfer component that extends from the first heat transfer component to or through the engine component, wherein the first heat transfer component comprises one of a heat pipe or a graphene rod, and wherein the second heat transfer component comprises the other of the heat pipe or the graphene rod.
    Type: Application
    Filed: June 16, 2022
    Publication date: November 2, 2023
    Inventors: Rajani Bhanu Poornima M, Vilas Kawaduji Bokade, Subramani Adhiachari, Sesha Subramanian, Pankaj Sharma, Ashish Sharma, Scott Alan Schimmels
  • Publication number: 20230315792
    Abstract: Data is collected from a network graph, wherein the collected data is useful for training a machine learning model on a query domain. A domain-specific template corresponding to the query domain is received, the domain-specific template defining one or more classifiers to guide collection of content relevant to the query domain from the network graph. A collection starting point is analyzed based on the one or more classifiers of the domain-specific template to identify one or more relevant instances of the content. The one or more identified relevant instances of the content are added to a contextual protocol package. Each identified relevant instance of the content is analyzed based on the one or more classifiers of the domain-specific template to identify one or more additional relevant instances of the content. The one or more identified additional relevant instances of the content are added to the contextual protocol package.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Yu ZHANG, Pankaj SHARMA, Manish SHUKLA, Grigoriy A. ORLOV
  • Publication number: 20230276624
    Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Pankaj Sharma, Naveen Kaushik, Sidhartha Gupta
  • Publication number: 20230187346
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Naveen Kaushik, Sidhartha Gupta, Pankaj Sharma, Haitao Liu