Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: An embedded system and an operating method thereof are disclosed. The embedded system comprises a micro-processor and a co-processor. The co-processor can only process non-interruptible instructions. The micro-processor is powered by an operating system to control the embedded system. When a task requires execution, the micro-processor appoints the co-processor to execute at least one batch command block. The batch command block is compiled with a sequence of non-interruptible instructions. When the task is complete, the co-processor outputs a response signal to the micro-processor.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: A method utilized in an electrical system is proposed. The electrical system includes a device, a host comprising a storage medium, and an interface interconnecting the device and the host. In an example of the proposed method, the device sends a buffer create request to the host. In response to the buffer create request, the host allocates a segment of the storage medium to the device. The device then utilizes the segment as an external buffer.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.

Abstract: Methods for performing ATAPI NCQ and ATAPI normal command are provided. The method involves receiving a predefined packet comprising essential information regarding a host command, the predefined packet received from a Serial ATA interface that is coupled to a host, wherein the essential information further indicates whether the command is a NCQ command; executing the command; and sending a completion packet to the host over the Serial ATA interface for indicating that the command was executed.

Abstract: A method of communicating with a serial advanced technology attachment (SATA) device by using a substitute SATA host comprises establishing a physical layer connection between the SATA device and the substitute SATA host; the substitute SATA host transmitting commands and data to the SATA device when a busy flag of the SATA device is set (BSY=1); and the SATA device communicating with the substitute SATA host in response to receiving the commands and data.

Abstract: A method of correcting corrupted primitives transmitted between a serial advanced technology attachment (SATA) host and a SATA device includes detecting the presence of a corrupted primitive; analyzing a current state, a previously transmitted primitive, or a previously received primitive; selecting at least one candidate primitive according to at least one of the current state, the previously transmitted primitive, and the previously received primitive; predicting the identity of the corrupted primitive according to at least one candidate primitive and the corrupted primitive; and replacing the corrupted primitive with the predicted primitive.

Abstract: A method involves receiving a first packet having a reference number, the first packet received from a Serial ATA interface that is coupled to a host; sending a first acknowledgement to the host over the Serial ATA interface; receiving a second packet having an ATAPI command from the host over the Serial ATA interface; sending a second acknowledgement to the host over the Serial ATA interface, the second acknowledgement indicating that a bit within said host should be cleared in order to indicate that said Serial ATA interface is no longer busy; sending a data transfer setup packet containing the reference number to the host over the Serial ATA interface; executing the command received from the host in the first packet; and sending a completion packet to the host over the Serial ATA interface for indicating that the command was executed.

Abstract: A SPI device. The SPI device comprises a serial clock pin, a chip select pin, a data input pin, and a data output pin. The serial clock pin transmits a serial clock from a master device to a slave device. The chip select pin determines whether the slave device is selected by the master device. The data input pin transfers instructions, addresses, data to be programmed, dummy input or a combination thereof from the master device to the slave device. The data output pin transfers data from the slave device to the master device. The SPI device acts as the master device or the slave device. One pin other than the data output, serial clock and chip select pins acts as an additional data output pin when the data output pin transfers data from the slave device to the master device.

Abstract: A signal generating circuit of a peripheral device for sending a frame information structure (FIS) to a host via a serial transmission channel to change a busy bit representing the state of the peripheral device. The signal generating circuit includes a trigger generator and a signal generator. The trigger generator generates a trigger signal by monitoring a control signal of the signal generating circuit. The signal generator, coupled to the trigger generator, generates the indication according to the trigger signal.

Abstract: A peripheral device for receiving a data frame containing control information from a serial transmission channel is disclosed. The peripheral device includes an information interpreter and a control unit. The information interpreter is coupled to the serial transmission channel, and used for receiving the data frame and interpreting the data frame to generate an operation signal according to the control information. The control unit is coupled to the information interpreter, and used for receiving the operation signal to execute an operation according to the control information.

Abstract: A microcontroller with expandable memory banks has a microprocessor, a plurality of memory banks with only one page for storing interrupt service routines(ISR), a memory bank control circuit connected to the microprocessor, and a multiplexer for connecting the microprocessor with the plurality of memory banks. The memory bank control circuit generates a selection signal according to an interrupt signal and a microprocessor interrupt service routine execution end signal. The multiplexer outputs a page selection signal from the microprocessor or outputs a predetermined page selection signal according to the output signal from the memory bank control circuit.

Abstract: A method for increasing the internal memory in a processor. The method includes providing an extended memory in the processor, adding bits to data addresses and register addresses with an address extender, and adding bits to stack addresses with a stack pointer generator so that the processor is capable of accessing memory addresses larger than the bit width of the command set of the processor. The method also includes carrying over the bits when the stack address exceeds the limit of the conventional memory and accessing the stack data exceeding the limit of the conventional memory in the extended memory.

Abstract: An electronic apparatus includes a controller having a serial AT Attachment (SATA) port. The controller is electrically coupled to a host through the SATA port. A plurality of peripheral devices are electrically coupled to the controller using digital means. The controller operates as a port multiplier to allow the host to access the peripheral devices through the SATA port. By using the digital means to connect the controller and the attached peripheral devices, no SATA ports or SATA cables are required and the cost of the electronic apparatus is therefore significantly reduced. The reduced number of SATA cables improves air movement and heat dissipation. The digital means can be designed to avoid complicated handshake operations between the controller and the peripheral devices, which improves latency and further increases the efficiency of the electronic apparatus.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated clock generation device generates a sampling clock signal according to a predetermined clock signal. The signal processor generates a plurality of detection results based on the sampling clock signal and the input signal. The logic determination device receives the plural of detection results and determines whether the input signal is the OOB signal.

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.