Abstract: A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet.

Abstract: A semiconductor chip-embedded circuit board and a fabrication method thereof are provided, including: a core board having first and second surfaces with first and second circuit layers thereon respectively, the first surface having a chip-receiving area (CRA); a laminated layer formed on the first and second surfaces and formed with an opening for exposing the CRA; third and fourth circuit layers formed on the laminated layer, the third circuit layer having first and second conductive pads, the fourth circuit layer having third conductive pads; a first insulating protective layer formed on the third circuit layer and formed with a plurality of first openings for exposing the first conductive pads and the CRA and a plurality of second openings for exposing the second conductive pads; and a second insulating protective layer formed on the fourth circuit layer and formed with third openings for exposing the third conductive pads. Mounting a semiconductor chip on the CRA reduces package height.

Abstract: The invention provides a circuit board structure for electrical testing and a fabrication method thereof.

Abstract: A metal electroplating process of an electrically connecting pad structure of a circuit board and structure thereof are proposed. First, a circuit board with a patterned circuit layer formed on at least one surface thereof is provided, wherein the circuit layer defines a plurality of electrically connecting pads and electroplating lines connected to the electrically connecting pads. Then, a patterned resist layer is formed on the circuit layer of the circuit board with the electroplating lines being covered by the patterned resist layer and the electrically connecting pads being exposed from the patterned resist layer. Subsequently, an electroplating process is performed so as to form a metal protection layer on the electrically connecting pads exposed from the patterned resist layer. Then, the resist layer is removed and a solder mask layer is formed on the circuit board.

Abstract: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a portion of the conductive film in an electrically connecting pad area intended for the circuit layer; removing a portion of the conductive film not covered with the resist; forming another resist on the substrate to cover a portion of the conductive film residually exposing from the resist; electroplating nickel/gold on at least one electrically connecting pad on the substrate such that the electrically connecting pad is electroplated with a nickel/gold layer; removing the resists and the conductive film thereunder; and forming a solder mask on the substrate, wherein the electrically connecting pad electroplated with the nickel/gold layer is exposed from the solder mask.