Patents by Inventor Paola Zuliani
Paola Zuliani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11462269Abstract: An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.Type: GrantFiled: November 16, 2020Date of Patent: October 4, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Giovanni Campardo, Massimo Borghi, Paola Zuliani, Marco Barboni
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Publication number: 20210166757Abstract: An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.Type: ApplicationFiled: November 16, 2020Publication date: June 3, 2021Inventors: Giovanni Campardo, Massimo Borghi, Paola Zuliani, Marco Barboni
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Patent number: 10903423Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.Type: GrantFiled: December 10, 2019Date of Patent: January 26, 2021Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.Inventors: Pierre Morin, Michel Haond, Paola Zuliani
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Patent number: 10706924Abstract: A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.Type: GrantFiled: April 24, 2019Date of Patent: July 7, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Giovanni Campardo, Roberto Annunziata, Paola Zuliani
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Publication number: 20200119269Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.Inventors: Pierre MORIN, Michel HAOND, Paola ZULIANI
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Patent number: 10510955Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.Type: GrantFiled: April 16, 2018Date of Patent: December 17, 2019Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.Inventors: Pierre Morin, Michel Haond, Paola Zuliani
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Publication number: 20190341103Abstract: A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.Type: ApplicationFiled: April 24, 2019Publication date: November 7, 2019Inventors: Giovanni Campardo, Roberto Annunziata, Paola Zuliani
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Publication number: 20180301625Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.Type: ApplicationFiled: April 16, 2018Publication date: October 18, 2018Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.Inventors: Pierre MORIN, Michel HAOND, Paola ZULIANI
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Patent number: 9991316Abstract: A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.Type: GrantFiled: December 9, 2016Date of Patent: June 5, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Paola Zuliani, Gianluigi Confalonieri, Annalisa Gilardini, Carlo Luigi Prelini
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Publication number: 20170373120Abstract: A phase-change memory cell, comprising: a substrate housing a transistor, for selection of the memory cell, that includes a first conduction electrode; a first electrical-insulation layer on the selection transistor; a first conductive through via through the electrical-insulation layer electrically coupled to the first conduction electrode; a heater element including a first portion in electrical contact with the first conductive through via and a second portion that extends in electrical continuity with, and orthogonal to, the first portion; a first protection element extending on the first and second portions of the heater element; a second protection element extending in direct lateral contact with the first portion of the heater element and with the first protection element; and a phase-change region extending over the heater element in electrical and thermal contact therewith.Type: ApplicationFiled: December 9, 2016Publication date: December 28, 2017Inventors: Paola ZULIANI, Gianluigi CONFALONIERI, Annalisa GILARDINI, Carlo Luigi PRELINI
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Publication number: 20110084247Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.Type: ApplicationFiled: December 16, 2010Publication date: April 14, 2011Inventors: Fabio Pellizzer, Roberto Bez, Paola Zuliani, Augusto Benvenuti
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Patent number: 7875513Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.Type: GrantFiled: April 26, 2006Date of Patent: January 25, 2011Inventors: Fabio Pellizzer, Roberto Bez, Paola Zuliani, Augusto Benvenuti
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Publication number: 20100163833Abstract: A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: STMicroelectronics S.r.I.Inventors: Massimo Borghi, Guido De Sandre, Fabio Pellizzer, Innocenzo Tortorelli, Paola Zuliani
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Patent number: 7663927Abstract: A reference voltage generator for a matrix of non-volatile memory cells of the EEPROM type, comprises at least one array enabled by an access transistor. The array comprises at least one reference cell associated with a relative select transistor, the transistors and the cell being realized on a semiconductor substrate and having active regions delimited by suitable field oxide regions and covered by a tunnel oxide layer and comprising at least one floating gate realized by a first polysilicon layer and covered by a dielectric layer and by a second polysilicon layer. Advantageously, the floating gate of the reference cells is contacted by a first contact terminal connected to a discharge transistor for the periodical discharge of possibly present charges. A process manufactures such a voltage generator.Type: GrantFiled: November 16, 2007Date of Patent: February 16, 2010Assignee: STMicroelectronics S.r.l.Inventors: Elisabetta Palumbo, Paola Zuliani, Roberto Annunziata, Daniele Zompi
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Patent number: 7649786Abstract: A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.Type: GrantFiled: January 31, 2007Date of Patent: January 19, 2010Assignee: STMicroelectronics S.r.l.Inventors: Antonino Conte, Roerto Annunziata, Paola Zuliani
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Patent number: 7483296Abstract: A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.Type: GrantFiled: September 22, 2005Date of Patent: January 27, 2009Inventors: Ferdinando Bedeschi, Fabio Pellizzer, Augusto Benvenuti, Loris Vendrame, Paola Zuliani
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Patent number: 7456467Abstract: A process for manufacturing a matrix of non volatile memory cells includes forming a floating gate transistor and a cell selection transistor in a first active area, and a byte selection transistor in a second active area. A multilayer structure is deposited, comprising a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer. The multilayer structure is defined to form two bands, the first band defining gate regions of the byte selection transistor and the cell selection transistor, and the second band defining the gate region of the floating gate transistor. A portion of the first band extends over a portion of insulating layer adjacent to the byte selection transistor. An opening is formed in the portion of the first band, exposing the first polysilicon layer, and a conductive layer is formed in the opening, electrically coupling the first polysilicon layer with the second polysilicon layer.Type: GrantFiled: October 25, 2005Date of Patent: November 25, 2008Inventors: Paola Zuliani, Elisabetta Palumbo, Marina Scaravaggi, Roberto Annunziata
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Publication number: 20080123404Abstract: A reference voltage generator for a matrix of non-volatile memory cells of the EEPROM type, comprises at least one array enabled by an access transistor. The array comprises at least one reference cell associated with a relative select transistor, the transistors and the cell being realized on a semiconductor substrate and having active regions delimited by suitable field oxide regions and covered by a tunnel oxide layer and comprising at least one floating gate realized by a first polysilicon layer and covered by a dielectric layer and by a second polysilicon layer. Advantageously, the floating gate of the reference cells is contacted by a first contact terminal connected to a discharge transistor for the periodical discharge of possibly present charges. A process manufactures such a voltage generator.Type: ApplicationFiled: November 16, 2007Publication date: May 29, 2008Applicant: STMICROELECTRONICS S.R.L.Inventors: Elisabetta Palumbo, Paola Zuliani, Roberto Annunziata, Daniele Zompi
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Publication number: 20070254446Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.Type: ApplicationFiled: April 26, 2006Publication date: November 1, 2007Inventors: Fabio Pellizzer, Roberto Bez, Paola Zuliani, Augusto Benvenuti
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Publication number: 20070247919Abstract: A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.Type: ApplicationFiled: January 31, 2007Publication date: October 25, 2007Inventors: Antonino Conte, Roberto Annunziata, Paola Zuliani