Patents by Inventor Paolo Cappelletti
Paolo Cappelletti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030235097Abstract: An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.Type: ApplicationFiled: May 30, 2003Publication date: December 25, 2003Applicant: STMicroelectronics S.r.I.Inventors: Emilio Camerlenghi, Paolo Cappelletti, Tecla Ghilardi, Mauro Sali, Giorgio Servalli
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Patent number: 6576950Abstract: The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.Type: GrantFiled: October 6, 2000Date of Patent: June 10, 2003Assignee: STMicroelectronics S.r.l.Inventors: Paolo Cappelletti, Alfonso Maurelli, Nicola Zatelli
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Patent number: 6532171Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.Type: GrantFiled: July 31, 2001Date of Patent: March 11, 2003Assignee: STMicroelectronics S.r.l.Inventors: Roberto Gastaldi, Paolo Cappelletti, Giulio Casagrande, Giovanni Campardo, Rino Micheloni
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Publication number: 20020140021Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.Type: ApplicationFiled: May 30, 2002Publication date: October 3, 2002Applicant: SGS-THOMSON MICROELECTRONICS S.R.L.Inventor: Paolo Cappelletti
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Patent number: 6410389Abstract: The memory cell is of the type with a single level of polysilicon, and is produced in a substrate of semiconductor material with a first type of conductivity, and comprises a control gate region with a second type of conductivity, formed in the substrate in a first active region; regions of source and drain with the second type of conductivity, formed in the substrate in a second active region; and a floating gate region which extends transversely relative to the first and the second active regions. The control gate region is surrounded by a first well with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well with the second type of conductivity. The regions of source and drain are accommodated in a second well with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well with the second type of conductivity.Type: GrantFiled: October 6, 2000Date of Patent: June 25, 2002Assignee: STMicroelectronics S.r.l.Inventors: Paolo Cappelletti, Alfonso Maurelli, Nicola Zatelli
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Patent number: 6399444Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.Type: GrantFiled: March 8, 2000Date of Patent: June 4, 2002Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Paolo Cappelletti
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Publication number: 20020041534Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.Type: ApplicationFiled: July 31, 2001Publication date: April 11, 2002Applicant: STMicroelectronics S.r.l.Inventors: Roberto Gastaldi, Paolo Cappelletti, Giulio Casagrande, Giovanni Campardo, Rino Micheloni
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Patent number: 6284585Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.Type: GrantFiled: August 31, 1999Date of Patent: September 4, 2001Assignee: STMicroelectronics S.r.l.Inventors: Emilio Camerlenghi, Paolo Cappelletti, Luca Pividori
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Patent number: 6275960Abstract: A method is for self-test and correction of errors due to a loss charge for a flash memory including an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided.Type: GrantFiled: December 16, 1998Date of Patent: August 14, 2001Assignee: STMicroelectronics S.r.l.Inventors: Paolo Cappelletti, Alfonso Maurelli, Marco Olivo
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Patent number: 6222775Abstract: A flash compatible EEPROM device has a first flash matrix and a second matrix with EEPROM functionalities of substantially similar layout. Both are divided into blocks of cells formed in substrate regions isolated from one another. In the second matrix, the information is organized in pages each contained in a row of memory cells of one of the blocks of subdivision of the matrix. A hierarchic structure including a row decoder addresses the wordline of all the cells of a selected row of the block, co-operating with a column decoder in selecting single cells of the rows. A boosted voltage of a polarity opposite to the supply voltage of the device is applied during an erasing phase to a single wordline selected by the row decoder, to page-erase the information by applying a boosted voltage to the common source of all the cells of the block and to the isolated region of the substrate containing all the cells of the block.Type: GrantFiled: June 21, 2000Date of Patent: April 24, 2001Assignee: STMicroelectronics S.r.l.Inventor: Paolo Cappelletti
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Patent number: 6172908Abstract: In order to optimize writing of the cell, the latter is written in a condition of equilibrium between an injection current Ig and the displacement current CppVsl. In this way, during writing, the voltage of the floating gate region Vfl remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage Vsb with respect to the source region, and the control gate region of the cell receives a ramp voltage Vcg with a selected predetermined inclination Vsl satisfying an equilibrium condition Vsl<Ig,sat/Cpp.Type: GrantFiled: October 8, 1998Date of Patent: January 9, 2001Assignee: STMicroelectronics S.r.l.Inventors: Paolo Cappelletti, Bruno Ricco, David Esseni
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Patent number: 6147380Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.Type: GrantFiled: March 8, 2000Date of Patent: November 14, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Paolo Cappelletti
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Patent number: 6101124Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.Type: GrantFiled: June 7, 1999Date of Patent: August 8, 2000Assignee: STMicroelectronics S.r.l.Inventors: Emilio Camerlenghi, Paolo Cappelletti, Luca Pividori
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Patent number: 6074916Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.Type: GrantFiled: October 1, 1998Date of Patent: June 13, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Paolo Cappelletti
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Patent number: 6054731Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.Type: GrantFiled: September 29, 1997Date of Patent: April 25, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Paolo Cappelletti
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Patent number: 5969977Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.Type: GrantFiled: December 29, 1997Date of Patent: October 19, 1999Assignee: STMicroelectronics S.r.l.Inventors: Emilio Camerlenghi, Paolo Cappelletti, Luca Pividori
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Patent number: 5942004Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.Type: GrantFiled: October 31, 1995Date of Patent: August 24, 1999Assignee: STMicroelectronics, S.r.l.Inventor: Paolo Cappelletti
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Patent number: 5926416Abstract: A device incorporating electrically programmable nonvolatile memory cells for a small number of programming cycles, in which an individual cell is impressed, both during the write step and the erase step, a bias condition such that a charge flow can only occur between the drain region and the gate dielectric, and vice versa.Type: GrantFiled: February 27, 1997Date of Patent: July 20, 1999Assignee: SGS - Thomson Microelectronics S.r.l.Inventors: Bruno Beverina, Paolo Cappelletti, Roberto Gastaldi
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Patent number: 5850092Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.Type: GrantFiled: April 10, 1997Date of Patent: December 15, 1998Assignee: SGS Thomson Microelectronics S.r.l.Inventor: Paolo Cappelletti
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Patent number: 5757719Abstract: A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of memory cells, memory page selection means for selecting a row of the matrix, and a plurality of sensing circuits each one associated with a respective column of the matrix. The memory cells are multiple-level memory cells which can be programmed in a plurality of c=2b(b>1) programming states to store b information bits, and the sensing circuits are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells, at each step one of said b information bits being determined, said at least one group of memory cells of a row forming a number b of memory words of a memory page.Type: GrantFiled: June 5, 1997Date of Patent: May 26, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Cristiano Calligaro, Roberto Gastaldi, Alessandro Manstretta, Paolo Cappelletti, Guido Torelli