Abstract: A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.

Abstract: A byte erasable memory with an EEPROM type functionality that can be integrated in a fully compatible way with a standard FLASH process is composed by a matrix of FLASH cells organized in n bytes, each of m bits, addressable through a plurality of wordlines and bitlines. The EEPROM-type memory has an auxiliary selection structure composed of an n number of byte select transistors, a plurality of individually selectable source biasing lines and a plurality of select lines in the same number of the wordlines and selectable in a biunivocal way with the wordlines. The cells of a byte have a common source that is accessed and individually selectable through the respective select transistor.

Abstract: A process which provides for the creation of regions of source and drain having different doping, wherein the doping, and thus the capacitance, of the drain regions is lower than that of the source regions.

Abstract: The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.