Patents by Inventor Paolo Crema

Paolo Crema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395680
    Abstract: A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 12125803
    Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: October 22, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Crema
  • Publication number: 20240332106
    Abstract: A semiconductor die is arranged at a first surface of a die pad. The die pad has a peripheral edge and a second surface opposite to the first surface that includes a first region and a second region surrounding the first region. The second region extends to the peripheral edge of the die pad from a border line at the first region and includes a recessed formation extending continuously along the border line. An insulating encapsulation is molded onto the die pad with the first region of the second surface left uncovered and the second region of the second surface of the die pad being covered by the insulating encapsulation that fills the recessed formation. The recessed formation has a variable recess depth between the border line and the peripheral edge of the die pad to provide an extended length delamination path from the border line to the semiconductor die.
    Type: Application
    Filed: March 25, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Paolo CREMA, Alberto ARRIGONI
  • Publication number: 20240249955
    Abstract: An multi-die semiconductor device disclosed herein includes a metallic leadframe with a central die pad encircled by electrically-conductive leads. Mounted on the die pad are two semiconductor dice, each with dedicated bonding pads on the surfaces facing away from the die pad. A layer of laser-activatable material is precisely molded over the dice and the leadframe. This layer forms a network of laser-activated lines: the first subset establishes electrical connections between the dice bonding pads and the leadframe leads, while the second subset interconnects the bonding pads of the first die to those of the second. There are two distinct metallic layers; the lower one, directly on the laser-activated lines, is formed of electroless-plated material, and the upper one, enhancing the structure, is formed of electroplated material, thus providing robust and reliable interconnections within the device.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Publication number: 20240179847
    Abstract: The present disclosure is directed to a method of forming a conductive trace in a substrate. A pattern of the trace is formed in the substrate by a laser machining technique. The pattern of the trace is covered by palladium colloid. The palladium colloid is transferred to the patterned substrate by a laser-induced forward transfer (LIFT) technique. The palladium colloid is converted to a palladium plating catalyst layer by a palladium acceleration process. The palladium plating catalyst layer provides a sufficient catalyst to grow a metal seeding layer by an electroless copper deposition technique. In addition, the palladium plating catalyst layer includes portions of tin material which increases adhesion of the metal seeding layer into the substrate. After growing the metal seeding layer, the pattern of the trace is filled by a copper layer through an electrochemical deposition technique.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 11977190
    Abstract: A device such as a dosimeter for detecting ionizing radiation, for example, X-ray radiation, in hospitals or the like. The device includes scintillator material configured to produce light as a result of radiation interacting with the scintillator material, and photoelectric conversion circuitry optically coupled to the scintillator material and configured to produce electrical signals via photoelectric conversion of light produced by the scintillator material. The device includes a plurality of photoelectric converters optically coupled with the scintillator material at spatially separated locations. The plurality of photoelectric converters thus produce respective electrical signals by photoelectric conversion of light produced by the scintillator material as a result of radiation interacting with the scintillator material. Improved energy linearity is thus facilitated while providing more efficient detection over the whole energy spectrum of radiation detected.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 7, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Sara Loi, Paolo Crema, Alessandro Freguglia
  • Publication number: 20240141543
    Abstract: Articles such as substrates for semiconductor products comprising metal and resin portions with adhesion promoter material are processed in a plating bath, wherein the adhesion promoter material is exposed to dissolution as a result of prolonged exposure to the plating bath. The articles are processed by dipping them in the processing bath so that they have opposed surfaces exposed to the processing bath. The movement of the articles through the processing bath B may occur to be halted. In that case a gas flow is provided lapping the opposed surfaces of the articles to shield the opposed surfaces of the articles from exposure to the processing bath.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 11948806
    Abstract: In a method of manufacturing a multi-die semiconductor device, a metal leadframe includes a die pad and electrically-conductive leads arranged around the die pad. First and second semiconductor dice are arranged on the die pad. A laser-activatable material is disposed on the dice and leads, and a set of laser-activated lines is patterned, including a first subset coupling selected bonding pads of the dice to selected leads, a second subset coupling selected bonding pads amongst themselves, and a third subset coupling the lines in the second subset to at least one line in the first subset. A first metallic layer is deposited onto the laser-activated lines to provide first, second and third subsets of electrically-conductive lines. A second metallic layer is selectively deposited onto the first and second subsets by electroplating to provide first and second subsets of electrically-conductive tracks. The electrically-conductive lines in the third subset are selectively removed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 2, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Crema
  • Patent number: 11869832
    Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Paolo Crema
  • Patent number: 11756899
    Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 12, 2023
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Paolo Crema, Jürgen Barthelmes, Din-Ghee Neoh
  • Publication number: 20230215819
    Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 6, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Publication number: 20230170283
    Abstract: A “double-deck” semiconductor device includes a first semiconductor chip mounted to a first surface of a leadframe, with a first wire bonding pattern and a first mass of encapsulating material molded onto the first surface of the leadframe when the leadframe is in a first spatial orientation. The leadframe with the first semiconductor chip and the first wire bonding pattern encapsulated and thus protected by the first mass of encapsulating material is then turned over to a second spatial orientation. A second semiconductor chip is attached to the second surface of the leadframe, with a second wire bonding pattern and a second mass of encapsulating material, different from the first mass of encapsulating material molded onto the second surface of the leadframe.
    Type: Application
    Filed: November 29, 2022
    Publication date: June 1, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 11640931
    Abstract: Manufacturing a semiconductor device, such as an integrated circuit, comprises: providing a leadframe having a die pad area, attaching onto the die pad area of the leadframe one or more semiconductor die or dice via soft-solder die attach material, and forming a device package by molding package material onto the semiconductor die or dice attached onto the die pad area of the leadframe. An enhancing layer, provided onto the leadframe to counter device package delamination, is selectively removed via laser beam ablation from the die pad area, and the semiconductor die or dice are attached onto the die pad area via soft-solder die attach material provided where the enhancing layer has been removed to promote wettability by the soft-solder material.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 2, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Paolo Crema
  • Publication number: 20230096480
    Abstract: A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 30, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 11610849
    Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 21, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Paolo Crema
  • Publication number: 20230002924
    Abstract: A uniform copper-tin compound layer is electrochemically deposited on a surface of a copper-based base structure. A tin-based film is then formed on the copper-tin compound layer. The uniform copper-tin compound layer provides a barrier that effectively inhibits tin whisker growth.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 5, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Publication number: 20220199426
    Abstract: In a method of manufacturing a multi-die semiconductor device, a metal leadframe includes a die pad and electrically-conductive leads arranged around the die pad. First and second semiconductor dice are arranged on the die pad. A laser-activatable material is disposed on the dice and leads, and a set of laser-activated lines is patterned, including a first subset coupling selected bonding pads of the dice to selected leads, a second subset coupling selected bonding pads amongst themselves, and a third subset coupling the lines in the second subset to at least one line in the first subset. A first metallic layer is deposited onto the laser-activated lines to provide first, second and third subsets of electrically-conductive lines. A second metallic layer is selectively deposited onto the first and second subsets by electroplating to provide first and second subsets of electrically-conductive tracks. The electrically-conductive lines in the third subset are selectively removed.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Publication number: 20210375787
    Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
    Type: Application
    Filed: May 17, 2021
    Publication date: December 2, 2021
    Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Paolo CREMA, Jürgen BARTHELMES, Din-Ghee NEOH
  • Publication number: 20210167022
    Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 3, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 11011476
    Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 18, 2021
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Paolo Crema, Jürgen Barthelmes, Din-Ghee Neoh