Patents by Inventor Para K. Segaram

Para K. Segaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low Profile Discrete Electronic Components and Applications of Same
    Publication number: 20100165525
    Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, William F. Wiedemann, Thomas J. Obenhuber, Inessa Obenhuber
  • High Speed, Direct Path, Stair-Step, Electronic Connectors with Improved Signal Integrity Characteristics and Methods for their Manufacture
    Publication number: 20100151704
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Application
    Filed: January 25, 2010
    Publication date: June 17, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram, Kevin P. Grundy
  • Multi-surface IC packaging structures and methods for their manufacture
    Patent number: 7737545
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: June 15, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy
  • Multi-surface contact IC packaging structures and assemblies
    Patent number: 7732904
    Abstract: A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: June 8, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber, legal representative, Kevin P. Grundy, William F. Wiedemann
  • Interconnect System without Through-Holes
    Publication number: 20100127402
    Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.
    Type: Application
    Filed: January 25, 2010
    Publication date: May 27, 2010
    Applicant: INTERCONNECT PORTFOLIO LLC
    Inventors: Kevin P. Grundy, Joseph C. Fjelstad, Gary Yasumura, William F. Wiedemann, Para K. Segaram
  • Low profile discrete electronic components and applications of same
    Patent number: 7701323
    Abstract: Disclosed are low profile discrete electronic component structures that are suitable for placement and use in a vertical interconnection mode either within an electronic interconnection substrate, between interconnection substrate and electronic component or within an IC package.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: April 20, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, William F. Wiedemann, Thomas J. Obenhuber, Inessa Obenhuber, legal representative
  • High speed, direct path, stair-step, electronic connectors with improved signal integrity characteristics and methods for their manufacture
    Patent number: 7651336
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram, Kevin P. Grundy
  • Interconnect system without through-holes
    Patent number: 7652381
    Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: January 26, 2010
    Assignee: Interconnect Portfolio LLC
    Inventors: Kevin P. Grundy, Joseph C. Fjelstad, Gary Yasumura, William F. Wiedemann, Para K. Segaram
  • Signal-segregating connector system
    Patent number: 7613011
    Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 3, 2009
    Assignee: Interconnect Portfolio LLC
    Inventors: Kevin P. Grundy, Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram
  • High-speed communication system with a feedback synchronization loop
    Patent number: 7593470
    Abstract: In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: September 22, 2009
    Assignee: Rambus Inc.
    Inventor: Para K. Segaram
  • Cabled Signaling System and Components Thereof
    Publication number: 20090120668
    Abstract: An assembly for conducting an electronic signal. The assembly includes a substrate and an electronic cable. The substrate has distinct first and second regions to enable connection to first and second circuit boards, respectively. First and second through-holes are formed in the substrate in the first and second regions, respectively. The electronic cable is disposed within the first through-hole and extends out of the first through hole, adjacent the substrate and into the second through-hole.
    Type: Application
    Filed: November 14, 2007
    Publication date: May 14, 2009
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Thomas Obenhuber, William F. Wiedemann
  • MEMORY CHAIN
    Publication number: 20090119464
    Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Inventors: Kevin P. Grundy, Para K. Segaram
  • DIRECT-CONNECT SIGNALING SYSTEM
    Publication number: 20090108416
    Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Belgacem Haba
  • Partitioned Integrated Circuit Package with Central Clock Driver
    Publication number: 20090091017
    Abstract: Disclosed are IC partitioned packaging and interconnection constructions that provide for improved distribution of power, ground, cross chip interconnections and clocks.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Thomas J. Obenhuber, Inessa Obenhuber
  • High Speed, Direct Path, Stair-Step, Electronic Connectors with Improved Signal Integrity Characteristics and Methods for their Manufacture
    Publication number: 20090093173
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Application
    Filed: October 8, 2007
    Publication date: April 9, 2009
    Inventors: Gary Yasumura, Joseph C. Fjelstad, William F. Wiedemann, Para K. Segaram, Kevin P. Grundy
  • TAPERED DIELECTRIC AND CONDUCTOR STRUCTURES AND APPLICATIONS THEREOF
    Publication number: 20090027137
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Application
    Filed: May 29, 2008
    Publication date: January 29, 2009
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Gary Yasumura
  • HIGH-SPEED COMMUNICATION SYSTEM WITH A FEEDBACK SYNCHRONIZATION LOOP
    Publication number: 20080273647
    Abstract: In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 6, 2008
    Applicant: Rambus Inc.
    Inventor: PARA K. SEGARAM
  • High speed communication system with a feedback synchronization loop
    Patent number: 7408995
    Abstract: In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: August 5, 2008
    Assignee: Rambus Inc.
    Inventor: Para K. Segaram
  • Tapered dielectric and conductor structures and applications thereof
    Patent number: 7388279
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 17, 2008
    Assignee: Interconnect Portfolio, LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Gary Yasumura
  • Memory chain
    Patent number: 7308524
    Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: December 11, 2007
    Assignee: Silicon Pipe, Inc
    Inventors: Kevin P. Grundy, Para K. Segaram